@kevlar
If you want an internal SMPS configuration, you do not normally need to manage PWR_ON, it only informs the power-up sequence condition where VDD and VDDA18AON have reached their POR threshold.
The first condition is to have VDD and VDDA18AON present first. Then if VDDSMPS (1.8V) is present and the external capacitor and inductance are connected, the internal SMPS will generate VDDCore at Startup.
I'm referring to AN5967 in STM32N6 power-up sequence:
Follow the steps below:
1. Apply VDD, VBAT, and VDD18AON.
2. If VDDCORE is supplied from an external SMPS step-down converter, apply VDDCORE when the PWR_ON
signal is high. Otherwise, VDDCORE is internally generated (refer to the section System supply startup and core
domain of the PWR section in the reference manual RM0486).
3. Then, apply the remaining power supplies in whatever order: VDDA18USB, VDD33USBCC, VDDA18CSI, VDDCSI, VDDA18ADC, VREF+, and VDDSMPS.
Concerning the grouping of the different supplies, here are a possible example you can follow:
Note: The domains can be grouped together as follows to simplify the power supply design:
• VDDCSI and VDDCORE.
• VDDA18PLL, VDDIO2, VDDIO3, VDDIO4, VDDIO5, and VDDA18AON.
• VDDA18USB, VDDA18CSI, VDDA18ADC, VREF+.
• VDD33USBCC and VDD33USB.
In your case you can design the power scheme below:
1x external DCDC or LDO 1.8V for VDDA18PLL, (optional VDDIO2, VDDIO3, VDDIO4, VDDIO5 if you need to operate at 1.8V), and VDDA18AON.
1x external DCDC or LDO 1.8V for VDDA18USB, VDDA18CSI, VDDA18ADC, VREF+.
1x external DCDC 1.8V dedicated for VDDSMPS (with high power)
1x external DCDC or LDO 3.3V for VDD, VDD33USBCC and VDD33USB and VDDIO2, VDDIO3, VDDIO4, VDDIO5 if you need to operate at 3.3V
Best regards,
Romain,