STM32N657xx Timer Clock(s)

Question

I am confused about which clock(s) drive the timers.  In the reference manual is says the APB clock drives the timers but there are 5 APB clocks.  Also, in STM32CubeMX there is a "Timer Group Clocks".  What clocks drive which timers or is the one drives all (Timer Group Clocks)?

Robert Ritchey · Accepted Answer

I was told by the support team at ST that this is not true. The "Timer Group Clocks" actually drive the timers.

"Yes, the clocks are connected PCLK1 and PCLK2, as shown in the reference manual. I know the term "Timer Group clocks" is vague, but I think we can deduce what it does by looking at the definition of TIMPRE register field:

Bits 25:24 TIMPRE[1:0]: Timer clock prescaler selection
This bitfield is security-protected by a SEC signal from RIFSC, the SYSSEC bit, a PRIV
signal from RIFSC, or the SYSPRIV bit, and is publicly readable if SYSPUB = 1. It is set and
reset by software to control the clock frequency of all the timers connected to APB1 and
APB2 domains.
00: timg_ck = sys_bus_ck (default after reset)
01: timg_ck = sys_bus_ck / 2
10: timg_ck = sys_bus_ck / 4
11: timg_ck = sys_bus_ck / 8"

Look at "Figure 45. Core and bus clock generation" for the divider and resultant timer clocks.

TDK · Answer

Go to the reference manual in the "Peripheral register boundary addresses" table and you can see which timer is within which APB.

The "timer group clock" is a separate clock you can use to clock individual timers. See timgx_ck below

It's also listed here which PCLK goes with which timer:

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