STM32U5 RAMCFG wait state config

[OneLine]

Hi, 

I'm currently using the STM32U575 to develop a product, and my clock configuration is set to the maximum of 160MHz because I'm dealing with a large amount of data. I have two SPI channels collecting data at a sampling rate of 20kHz, with each sampling returning 70 data points. During operation, I encounter Hardfaults on the bus, with bus fault information showing IBUSERR or PRECISERR. I suspect that the CPU and DMA are competing for the bus, causing errors. However, I found that by adjusting the wait state parameter in the RAMCFG configuration to 1 or 2, the system runs much more stably. Is RAM access unstable at 160MHz? Do you have any experience with configuring RAM wait states, or how to ensure reliable operation?

[STOne-32]

Dear @OneLine ,

you can refer to slide 8 here 

https://www.st.com/content/ccc/resource/training/technical/product_training/group1/43/52/da/40/97/e8/44/da/STM32U5-Memory-RAM-CFG_RAMCFG/files/STM32U5-Memory-RAM-CFG_RAMCFG.pdf/_jcr_content/translations/en.STM32U5-Memory-RAM-CFG_RAMCFG.pdf

if your configuration case is not inline , it is not normal and we never had such issue , you may check the race conditions from different masters writing on same memory . If possible to know if particular addresses are impacted ? To identify which RAM .

hope it helps ,

STOne-32