STM32U575: OCTOSPIM_P1_DQS in SDR mode?

[tjaekel]

I will use the STM32U575 with OCTOSPIM as Quad SPI (master) adapter.

Q: The DQS signal is intended for DDR mode (I know).
Could I use also DQS as input in SDR mode (when OCTOSPIM acts as SPI or QSPI master)?

Idea:
I want to compensate the "Round Trip Delay" on QSPI (or OCTOSPIM as SPI).
Could I provide a SCLK' signal via DQS (delayed, with external DLY line) so that the READ cycle will use this signal in order to sample the response bits?

Or is DQS only "working" in DDR mode (even I would 'enable' DQS also in SDR mode)?

Quad-SPI in SDR mode should use DQS with external delay in order to sync D[3..0] during a READ transactions. Is it possible? (feedback SCLK with a delay line to DQS)

[KDJEM.1]

Hello @tjaekel and welcome to the Community :),

To check your request, could you please give more detail about the slave:

Which slave are you using in this case? Is it a memory?

Could you please share the datasheet of this slave device?

Does the SSHIFT function suit you in this case?

Note that  SSHIFT: can be enabled when reading from the memory in SDR mode but must not be used in DTR mode. When enabled, the sampling is delayed by one more 1/2 OCTOSPI/HSPI clock cycle enabling more relaxed input timings.

Thank you.

Kaouthar

[tjaekel]

Hi KDJEM.1,

I cannot disclose for which chip it will be: just: I need QSPI for testing another chip with a QSPI interface.
It is not a memory chip (QSPI as access to chip registers, data FIFOs inside ...).

Yes, SSHIFT, I will use, for sure. It will give me (additional) 1/2 clock cycle delay to compensate the "delayed response" from remote chip. Read sample clock should be already the next half-clock-cycle edge.

Issue/idea is:
we will have a longer cable (e.g. the chip sits in an oven for temperature testing). There is also a need to have level shifters (QSPI slave is 1V8 logic). And the chip has internal gates which would "delay the response". With 25 MHz QSPI clock, I have 1/2 clock cycle to sample still properly the read response. This is 40 ns. The propagation delay plus the delays due to level shifters, logic gates can reach easily this timing constraints.

Therefore, I want to use an approach, I call it "DualSPI", used on regular SPI, also for QSPI: SPI Tx is a master but the SCLK is fed back from remote side to a SPI Rx slave. This compensates the "round trip delay". So, I thought, I could do something similar with QSPI: the DQS signal is the SCLK signal "mirrored back" from the slave side, also delayed in the same way through level shifters (delaying DIO data lanes). So, if DQS would be used as the SLK' clock during a read phase, also in SDR mode, it would do what I would need: it could compensate the "round trip delay", independent of the 1/2 clock cycle (and could be even larger, e.g. 100 ns for SCLK to SCLK' delay).

The SSHIFT will help me a bit, when adding additional 1/2 clock cycle (so that I have now 80 ns window for sampling read response, minus the setup time).

I will see. It was just idea if DQS would work in a similar way to be used a Read SCLK' (as I do with my SPI Rx as slave for a bi-directional SPI).

Thank you.

[KDJEM.1]

Hello @tjaekel ,

There are no restrictions to use DQS in Quad-Spi mode.

However, you should pay attention to the correspondence between all phases and to the number of cycles in the different phase (command, address, dummy).

Thank you.

Kaouthar

[tjaekel]

Great,

I will test it and let you know. I have designed a PCB board with a STM32U575 where I bring out the DQS signal (for this purpose and to test).

Thank you.

[KDJEM.1]

Hello @tjaekel ,

Thank you for your contribution in STCommunity and please let me know the results of the tests. :).

If your question has been answered, please close this topic by choosing Accept as Solution. This will help other users find that answer faster. 

Thank you.

Kaouthar

[tjaekel]

Update:

I tried OCTOSPI_DQS signal:
when I do the read phase - I enable DQS (I am running SDR mode):
What happens is:
- the read phase never finishes
- on scope I see so many SCK signals generated without to complete the read transaction

But I have to debug further, just a first simple approach as: when read phase - do it with DQS enabled. (I have to understand this DQS signal a bit better and study the datasheet). I'll come back to the topic (I need to bringup USB on a STM32U575 chip first).