STM32U575: Watchdog reset when exit from STOP3 mode.

[SMill.8]

Hello,

in my application, exiting from STOP3 mode is working fine but when the SRAM is over 192K, so getting SRAM2 addresses, exiting from STOP3 mode is forcing watchdog reset (I think when is trying to access a variable placed on SRAM2)  however from STOP2 mode is working fine.

In STM32IDE debug mode everything is working fine too, so I´m totally blind and I can´t get any clue in the reference manual.

Anyone could help me, please?

 

Thank you.

[CMYL]

Hello @SMill.8 

Can give more details/pseudo code of the entry and the exit sequences ? What is the wake up source ? 

 

BR

YL

[SMill.17]

Hi,@CMYL

The micorcontroller is a STM32U575CI.

The wake up source are or RTC or one of the following EXTI pins.

This is code of the entry and the exit sequences.

 HAL_PWR_EnableWakeUpPin(PWR_WAKEUP_PIN7_HIGH_3);
HAL_PWR_EnableWakeUpPin(PWR_WAKEUP_PIN2_HIGH_1);
HAL_PWR_EnableWakeUpPin(PWR_WAKEUP_PIN1_HIGH_0);
HAL_PWR_EnableWakeUpPin(PWR_WAKEUP_PIN7_HIGH_1);
HAL_PWR_EnableWakeUpPin(PWR_WAKEUP_PIN8_HIGH_1);

 

HAL_SuspendTick();

 

HAL_PWREx_EnableRAMsContentStopRetention(PWR_SRAM1_FULL_STOP);

HAL_PWREx_EnableRAMsContentStopRetention(PWR_SRAM2_FULL_STOP);

HAL_PWREx_EnableRAMsContentStopRetention(PWR_SRAM3_FULL_STOP);

HAL_PWREx_EnableRAMsContentStopRetention(PWR_SRAM4_FULL_STOP);

HAL_PWREx_EnableRAMsContentStopRetention(PWR_ICACHE_FULL_STOP);

HAL_PWREx_EnableRAMsContentStopRetention(PWR_DMA2DRAM_FULL_STOP);

/* STOP3 wake up global interrupt configuration */

HAL_NVIC_SetPriority(PWR_S3WU_IRQn, 7, 7);

HAL_NVIC_EnableIRQ(PWR_S3WU_IRQn);

/** STOP3 MODE WFI */

HAL_PWREx_EnterSTOP3Mode(PWR_STOPENTRY_WFI);

 

/** WAKES UP FROM STOP3 MODE  */

SystemInit();

SystemCoreClockUpdate();

SystemClock_Config();

 

/* Resume tick interruptions */

HAL_ResumeTick();

 

HAL_NVIC_DisableIRQ(PWR_S3WU_IRQn);

 

if (HAL_IWDG_Refresh(&hiwdg) != HAL_OK)
{
/* Refresh Error */
Error_Handler();
}

 

And here I access to a SRAM2 variable and triggers a Hard Fault.

 

If you need more information, do not hesitate to ask.

 

Best regards.

 

SM

[CMYL]

Thank you, I'm working on to reproduce the issue 

[CMYL]

Hi @SMill.17 

I followed your sequence of code to enter or exit the STOP 3. I'm still not able to reproduce the issue.

In my opinion, what is missing in this code is the setting SRAM wait states to 1 after wakeup at 24 Mhz. In RM0456 (section 6.3.4 Read access latency, Table 47. Number of wait states versus HCLK frequency and voltage range scaling), the WS must be 1 when VOS is range 4, 24 Mhz. This can be programmed in WSC[2:0] field of RAMCFG_MxCR.

However, to confirm this hypothesis, can you update your code by configuring the system clock to MSI @16 Mhz, with 16 Mhz no changes required for SRAM latency (0 WS). Then check if you still fall into a hardfault.

One other point, SystemClock_Config() as implemented by the HAL requires SysTick. So you need to revert the calling order of  SystemClock_Config(); and HAL_ResumeTick();. Otherwise, the tick count inside this function can cause the IWDG reset.

Can you try these suggestions, if not helpful we will go indepth into the code details.

Some other comments of the code :

- In STOP3, SysTick is not functional (table 100 of RM), then no need to suspend the SysTick in stop modes.

- SystemInit() and SystemCoreClockUpdate() APIs are needed at boot. You can remove them after wakeup.  

    /** WAKES UP FROM STOP3 MODE  */

   SystemInit();

   SystemCoreClockUpdate();

[SMill.17]

Thank you very much for your quick response. I´ll try all your suggestions and be back to you.

 

Best regards.

[SMill.17]

Hi again

Just one question,

below you can see SystemClock_Config() code. Actually I think I was already configuring wait states to 1 after wakeup with this call at the end of the function:

 

if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)

 

Is this right?

 

/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};

/** Configure the main internal regulator output voltage
*/
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE3) != HAL_OK)
{
Error_Handler();
}

/** Configure LSE Drive Capability
*/
HAL_PWR_EnableBkUpAccess();
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMLOW);

/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_LSE
|RCC_OSCILLATORTYPE_MSI|RCC_OSCILLATORTYPE_MSIK;
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_0;
RCC_OscInitStruct.LSIDiv = RCC_LSI_DIV1;
RCC_OscInitStruct.MSIKClockRange = RCC_MSIKRANGE_0;
RCC_OscInitStruct.MSIKState = RCC_MSIK_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
}

/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
|RCC_CLOCKTYPE_PCLK3;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;

if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
{
Error_Handler();
}

/** Enables the Clock Security System
*/
HAL_RCCEx_EnableLSECSS();
}

 

Thank you.

 

Best regards.

[CMYL]

Hi @SMill.17 

You are configuring the Flash Latency in SystemClock_Config(). SRAM wait state is configured by RAMCFG, it is explained more later below.

Your  System clock is 48 Mhz (the source is MSI, the MSI clock range is 0 as RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_0; and the divider is div1). 

HCLK and PCLK are also 48 Mhz as the AHB/APB dividers are div1. Flash Latency is 1 as you are in voltage scaling 3.

My test request in the comment above is to configure the clock frequency at 16 Mhz. the MSI configuration is as follow: RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_2;. A code sample is attached.  

With 16 Mhz, the voltage scaling range is 4. In this case, the SRAM WS can be 0, so you should not see any hardfault. This test is to confirm that the issue is not due to SRAM WS configuration.

In more details, the SRAM wait state can be configured by RAMCFG peripheral which is the controller that manages SRAM erase, ECC, read access latency ... among others. 

To correctly read data from SRAMs, the number of wait states must be correctly programmed in WSC[2:0] field of RAMCFG_MxCR, depending on AHB clock frequency (HCLK) and voltage scaling range, as shown in the table below.

If you are using HAL, you need to call the following API after enabling the RAMCFG peripheral.

HAL_RAMCFG_ConfigWaitState(&hramcfg_SRAM1, RAMCFG_WAITSTATE_1);

You can also follow the snapshot below of the STM32CubeMx code generator to configure SRAM WS.

 

Best Regards,

Younes

 

[SMill.17]

Hello,

 

I tried what you suggest me with no success.

This is MX_RAMCFG_Init function I´m using, calling it at system initialization and after STOP3 mode. I tried lowering clock to 16MHz with no wait states also.

/**
* @brief RAMCFG Initialization Function
* @PAram None
* @retval None
*/
void MX_RAMCFG_Init(void)
{

/* USER CODE BEGIN RAMCFG_Init 0 */

/* USER CODE END RAMCFG_Init 0 */

/* USER CODE BEGIN RAMCFG_Init 1 */

/* USER CODE END RAMCFG_Init 1 */

/** Initialize RAMCFG SRAM1
*/
hramcfg_SRAM1.Instance = RAMCFG_SRAM1;
if (HAL_RAMCFG_Init(&hramcfg_SRAM1) != HAL_OK)
{
Error_Handler();
}
if (HAL_RAMCFG_StopECC(&hramcfg_SRAM1) != HAL_OK)
{
Error_Handler();
}
HAL_RAMCFG_ConfigWaitState(&hramcfg_SRAM1, RAMCFG_WAITSTATE_1);
/** Initialize RAMCFG SRAM2
*/
hramcfg_SRAM2.Instance = RAMCFG_SRAM2;
if (HAL_RAMCFG_Init(&hramcfg_SRAM2) != HAL_OK)
{
Error_Handler();
}
if (HAL_RAMCFG_StopECC(&hramcfg_SRAM2) != HAL_OK)
{
Error_Handler();
}
HAL_RAMCFG_ConfigWaitState(&hramcfg_SRAM2, RAMCFG_WAITSTATE_1);
/** Initialize RAMCFG SRAM3
*/
hramcfg_SRAM3.Instance = RAMCFG_SRAM3;
if (HAL_RAMCFG_Init(&hramcfg_SRAM3) != HAL_OK)
{
Error_Handler();
}
if (HAL_RAMCFG_StopECC(&hramcfg_SRAM3) != HAL_OK)
{
Error_Handler();
}
HAL_RAMCFG_ConfigWaitState(&hramcfg_SRAM3, RAMCFG_WAITSTATE_1);
/** Initialize RAMCFG SRAM5
*/
hramcfg_SRAM4.Instance = RAMCFG_SRAM4;
if (HAL_RAMCFG_Init(&hramcfg_SRAM4) != HAL_OK)
{
Error_Handler();
}
HAL_RAMCFG_ConfigWaitState(&hramcfg_SRAM4, RAMCFG_WAITSTATE_1);
/* USER CODE BEGIN RAMCFG_Init 2 */

/* USER CODE END RAMCFG_Init 2 */

}

 

Thank you very much.

 

Best regards.

 

Sergio.

[CMYL]

Can you share your source code, just the core "src+inc directories" ?

Best Regards,

 

[SMill.17]

Hi,

it´s a .7z file, you have to rename .c to .zip to uncompress.

Anything you need to clarify, do not hesitate to ask.

Thank you very much.

Best regards.

[SMill.17]

Sorry, finally I sent files in a 7z compressed file. Forget about .c and renaming

[CMYL]

Hello @SMill.17,

I'm actively working on the issue, I let you know.

best Regards