STM32U599 OC Tim DMA failed start or do some toggle

[MM..1]

We try generate signal defined by toggle table , but command do nothink. (except ARR toggles)

 if (HAL_TIM_OC_Start_DMA(&htim2, TIM_CHANNEL_4, &tim_values[0], idx) != HAL_OK)
 {
 Error_Handler();
 }

have 1.7.0 U5 firmware some known issue ? Or what is required to right setup this.

We try add enable GPDMA etc. No change. For ARR is one toggle no based on table. Seems we skip some trigger setup or U5 HAL is buggy .? Pls help. Simply we have table and require toggle for example 20 words table in time.

Actual config:

main ...
 /* Initialize all configured peripherals */
 MX_GPDMA1_Init();
 MX_CRC_Init();
 MX_RAMCFG_Init();
 MX_DSIHOST_DSI_Init();
 MX_LTDC_Init();
 MX_TIM3_Init();
 MX_USART2_UART_Init();
 MX_DCACHE1_Init();
 MX_ICACHE_Init();
 MX_DMA2D_Init();
 MX_GPU2D_Init();
 MX_DCACHE2_Init();
 MX_TIM2_Init();
 MX_TouchGFX_Init();
 /* Call PreOsInit function */


static void MX_TIM2_Init(void)
{

 /* USER CODE BEGIN TIM2_Init 0 */

 /* USER CODE END TIM2_Init 0 */

 TIM_ClockConfigTypeDef sClockSourceConfig = {0};
 TIM_MasterConfigTypeDef sMasterConfig = {0};
 TIM_OC_InitTypeDef sConfigOC = {0};

 /* USER CODE BEGIN TIM2_Init 1 */

 /* USER CODE END TIM2_Init 1 */
 htim2.Instance = TIM2;
 htim2.Init.Prescaler = 159;
 htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
 htim2.Init.Period = 1000000;	//4294967295;
 htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
 htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
 if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
 {
 Error_Handler();
 }
 sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
 if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
 {
 Error_Handler();
 }
 if (HAL_TIM_OC_Init(&htim2) != HAL_OK)
 {
 Error_Handler();
 }
 sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
 sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
 if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
 {
 Error_Handler();
 }
 sConfigOC.OCMode = TIM_OCMODE_TOGGLE;
 sConfigOC.Pulse = 0;
 sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
 sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
 if (HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
 {
 Error_Handler();
 }
 /* USER CODE BEGIN TIM2_Init 2 */
// HAL_TIM_OC_Start(&htim2,TIM_CHANNEL_4);
 /* USER CODE END TIM2_Init 2 */
 HAL_TIM_MspPostInit(&htim2);
}

void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
 if(htim_base->Instance==TIM2)
 {
 /* USER CODE BEGIN TIM2_MspInit 0 */

 /* USER CODE END TIM2_MspInit 0 */
 /* Peripheral clock enable */
 __HAL_RCC_TIM2_CLK_ENABLE();

 /* TIM2 DMA Init */
 /* GPDMA1_REQUEST_TIM2_CH4 Init */
 handle_GPDMA1_Channel0.Instance = GPDMA1_Channel0;
 handle_GPDMA1_Channel0.Init.Request = GPDMA1_REQUEST_TIM2_CH4;
 handle_GPDMA1_Channel0.Init.BlkHWRequest = DMA_BREQ_SINGLE_BURST;
 handle_GPDMA1_Channel0.Init.Direction = DMA_MEMORY_TO_PERIPH;
 handle_GPDMA1_Channel0.Init.SrcInc = DMA_SINC_INCREMENTED;
 handle_GPDMA1_Channel0.Init.DestInc = DMA_DINC_FIXED;
 handle_GPDMA1_Channel0.Init.SrcDataWidth = DMA_SRC_DATAWIDTH_WORD;
 handle_GPDMA1_Channel0.Init.DestDataWidth = DMA_DEST_DATAWIDTH_WORD;
 handle_GPDMA1_Channel0.Init.Priority = DMA_LOW_PRIORITY_HIGH_WEIGHT;
 handle_GPDMA1_Channel0.Init.SrcBurstLength = 1;
 handle_GPDMA1_Channel0.Init.DestBurstLength = 1;
 handle_GPDMA1_Channel0.Init.TransferAllocatedPort = DMA_SRC_ALLOCATED_PORT0|DMA_DEST_ALLOCATED_PORT0;
 handle_GPDMA1_Channel0.Init.TransferEventMode = DMA_TCEM_BLOCK_TRANSFER;
 handle_GPDMA1_Channel0.Init.Mode = DMA_NORMAL;
 if (HAL_DMA_Init(&handle_GPDMA1_Channel0) != HAL_OK)
 {
 Error_Handler();
 }

 __HAL_LINKDMA(htim_base, hdma[TIM_DMA_ID_CC4], handle_GPDMA1_Channel0);

 if (HAL_DMA_ConfigChannelAttributes(&handle_GPDMA1_Channel0, DMA_CHANNEL_NPRIV) != HAL_OK)
 {
 Error_Handler();
 }

 /* TIM2 interrupt Init */
 HAL_NVIC_SetPriority(TIM2_IRQn, 5, 0);
 HAL_NVIC_EnableIRQ(TIM2_IRQn);
 /* USER CODE BEGIN TIM2_MspInit 1 */
 LL_DMA_EnableChannel(GPDMA1,LL_DMA_CHANNEL_0);
 /* USER CODE END TIM2_MspInit 1 */
 }
 else if(htim_base->Instance==TIM3)
 {
 /* USER CODE BEGIN TIM3_MspInit 0 */

 /* USER CODE END TIM3_MspInit 0 */
 /* Peripheral clock enable */
 __HAL_RCC_TIM3_CLK_ENABLE();
 /* USER CODE BEGIN TIM3_MspInit 1 */

 /* USER CODE END TIM3_MspInit 1 */
 }
 else if(htim_base->Instance==TIM15)
 {
 /* USER CODE BEGIN TIM15_MspInit 0 */

 /* USER CODE END TIM15_MspInit 0 */
 /* Peripheral clock enable */
 __HAL_RCC_TIM15_CLK_ENABLE();
 /* USER CODE BEGIN TIM15_MspInit 1 */

 /* USER CODE END TIM15_MspInit 1 */
 }

}

void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
 GPIO_InitTypeDef GPIO_InitStruct = {0};
 if(htim->Instance==TIM2)
 {
 /* USER CODE BEGIN TIM2_MspPostInit 0 */

 /* USER CODE END TIM2_MspPostInit 0 */
 __HAL_RCC_GPIOB_CLK_ENABLE();
 /**TIM2 GPIO Configuration
 PB11 ------> TIM2_CH4
 */
 GPIO_InitStruct.Pin = OC_Pin;
 GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
 GPIO_InitStruct.Pull = GPIO_PULLUP;
 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
 GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
 HAL_GPIO_Init(OC_GPIO_Port, &GPIO_InitStruct);

 /* USER CODE BEGIN TIM2_MspPostInit 1 */

 /* USER CODE END TIM2_MspPostInit 1 */
 }
 else if(htim->Instance==TIM3)
 {
 /* USER CODE BEGIN TIM3_MspPostInit 0 */

 /* USER CODE END TIM3_MspPostInit 0 */

 __HAL_RCC_GPIOE_CLK_ENABLE();
 /**TIM3 GPIO Configuration
 PE3 ------> TIM3_CH1
 */
 GPIO_InitStruct.Pin = LCD_LED_Pin;
 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 GPIO_InitStruct.Pull = GPIO_NOPULL;
 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
 HAL_GPIO_Init(LCD_LED_GPIO_Port, &GPIO_InitStruct);

 /* USER CODE BEGIN TIM3_MspPostInit 1 */

 /* USER CODE END TIM3_MspPostInit 1 */
 }

}

 

[waclawek.jan]

If DMA would not work, you should see the output to toggle at the ARR rate anyway. So is that what is happening?

Read out and check/post content of TIM and DMA registers, perhaps at the moment when it already has been started but does not work as expected. Also, show us the array you are transferring using DMA.

Note, that if you want the "walking toggle" i.e. your array consists of values with small differences, all of them to be used within one ARR period, then you have to make sure the TIMx_CCRx is not preloaded, i.e. the respective TIMx_CCMRx.OCxPE has to be 0. I don't know how this is done in Cube, I don't use Cube.

JW

[MM..1]

Yes i write this ARR toggles = normal when CCR is constant in real toggles CCR. Yes debuger show all aka ok, but no real work. xPE is 0 DIER CC4DE is only 1 mode 0x3 and if manualy insert CC4=10000; before dma line one 10ms pulse is ok generated , but nothing next from DMA and repeat only ARR time...

 

[waclawek.jan]

So if TIM works as expected, the problem is probably at the DMA side.

The 'U5 GPDMA is very different from the older STM32 DMAs and I don't know it, but generally, looking at the DMA registers and checking them against expected values according to the reference manual should give a clue.

JW

[MM..1]

Then solution:

1. HAL mistake is name of func 

HAL_TIM_OC_Start_DMA

 realy start nothink. OC set bit for DMA req on first CCR compare, but first value from table isnt preloaded = if start with 32bit ARR max then for some PSC can wait years for real start after CNT reach CCR...

2. HAL mistake is after end of DMA count stay OC in BUSY and no other DMA can start, require absurd STOP. And cant restart next dma packet in complete callback ...

3. HAL mistake is last Length parameter in DMA. Here seems must be in bytes = x4 for WORDS in DMA.