STM32U5A5 Hard fault setting SYSCLK > 64Mhz

[moylando]

I'm trying to crank up the clock to Timer1 to be able to count high frequency events with better resolution.  If I set the SYSCLK to 128 I get a hard fault when my code reaches SystemClock_Config().  Even if I keep the AHB bus at the same speed (64Mhz) using prescaler.  In this case the only clock difference seems to be SYSCLK value.

Here's the first configuration which works ok:

and here's the other where it will hard fault:

Since the IDE says I should be able to take HCLK to 160Mhz which would require a much higher SYSCLK, I don't see why this SYSCLK value should cause a fault.

[TDK]

Is this custom hardware? Ensure power rails and decoupling capacitors and other power supply infrastructure is functioning correctly. Show the schematic if you can.

Step through SystemClock_Config to see where it hard faults, and/or look at the hard fault to shed light on what may be failing.

[moylando]

Hey, thanks for the reply.  It's a Nucleo-U5A5ZJ-Q.  Not custom.

Here's a backtrace:

a HAL_GetTick() is called after modifying RCC->CFGR1

[moylando]

And here's some fault analyzer output:

 

[moylando]

I've had some luck stepping up the PLL frequency in steps.  

So far, I've been able to get the SYSCLK up to 112Mhz.  Will keep experimenting.

[moylando]

Yes, 112Mhz seems to be the max, but it's working with HCLK = 112Mhz also, when it doesn't work with SYSCLK = 128Mhz and HCLK = 64Mhz via the divider.  I don't have SYSCLK being used by any peripherals so unsure why there would be any sensitivity to it.

[AScha.3]

Hey, you have an U5A5 cpu, so set it to 160M.

Look at the power supply setting first, it has to be on range 1 :

+

How you made the Cube/ioc ? New , or starting from a fixed "board" ?

[moylando]

This section from page 411 of the ref manual has me curious:

The wording here is a bit unclear.  When it says 'system frequency' are we talking about SYSCLK or AHB?  Seeing as they recommend using the AHB prescaler I would think that's what they're referring to.  However, in my case, fixing it to /2 which brings the AHB within this range (SYSCLK=128, AHB=64) doesn't seem to make a difference.  Could this limitation apply to SYSCLK?  I've verified the VOS range is 1 (CubeIDE sets this depending on the initial SYSCLK configuration)

[moylando]

@AScha.3, I'm starting from the specific board configuration in CubeIDE.

[AScha.3]

So, if this CPU really cannot start at its full speed, set ahb as told to 2, and sysclock to 160M. So it's starting at 80M .

Then in program do the switching to 160 by writing the ahb prescaler to 1.

Then it should run at max speed .

 

[moylando]

No, doesn't work.  Any setting with SYSCLK > 112Mhz does not work.  I've tried 160Mhz with multiple AHB prescalers (not even upping the AHB frequency later, so AHB stays lower) and it seems totally insensitive.  The only factor I've been able to deduce is the SYSCLK setting.

[moylando]

I added this block between enabling the PLL and updating RCC clock config (which are both done in the code generated by CubeIDE).  I did this because I noticed in the registers that the BOOSTRDY flag was not set:

 uint32_t timeout;
 timeout = ((0x64U * (SystemCoreClock / 1000U)) / 1000U) + 1U;
 while (HAL_IS_BIT_CLR(PWR->VOSR, PWR_VOSR_BOOSTRDY) && (timeout != 0U))
 {
 timeout--;
 }

 if (timeout == 0U)
 {
 Error_Handler();
 }

This did manage to wait correctly for the flag to be set before proceeding, but unfortunately made no difference at SYSCLK = 128Mhz.

[Tesla DeLorean]

Power Supply, lack of adequate bulk capacitance on the supply side, or at VCAP pin(s)

Flash Wait States / Latency

Caching or Prefetch settings

[moylando]

Changed this auto generated code:

 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
 {
 Error_Handler();
 }

from LATENCY_1 to LATENCY_2 and it's now running at SYSCLK=128 / HCLK = 64

According to this doc:

https://www.st.com/content/ccc/resource/training/technical/product_training/group1/95/d2/99/8c/32/75/40/6b/STM32U5-Memory-FLASH_FLASH/files/STM32U5-Memory-FLASH_FLASH.pdf/_jcr_content/translations/en.STM32U5-Memory-FLASH_FLASH.pdf  Page 7  it should be OK with LATENCY_1 upto 64Mhz.

Not sure why that won't work.  Will keep experimenting with increasing clock frequency.

[Tesla DeLorean]

Other STM32 the FLASH max clock is ~27 MHz (or around 35ns), but can be quite wide

LATENCY_2 is basically 3-cycle memory

Speed of FLASH also a function of Voltage, slower at low voltages