STM32U5A9 Octal SPI with octal flash in DTR mode

[Sanath]

Hi Team,

 

I am working on STM32U5A9J-DK for one of our applications interfaces with an Octal flash via Octal SPI.

we were able to communicate and do the flash operations Read write using the SDR mode .

Now to achieve the DTR mode from STM32U5a9 end what are the initial setting we need to go through or make?

We have a register in Octal flash to set it in Octal DDR mode, but do we need to set anything from STM32 end to change? 

 

Regards

Sanath

[Tesla DeLorean]

MX25UM51245GXDI00

https://www.macronix.com/Lists/Datasheet/Attachments/8967/MX25UM51245G,%201.8V,%20512Mb,%20v1.5.pdf

You'd need to use command 8DTRD 0xEE / 0xEE11

https://github.com/STMicroelectronics/stm32-mx25um51245g/blob/2fdc96a372222d6a3e47fb84263e176636a68972/mx25um51245g.c

https://github.com/STMicroelectronics/stm32-mx25um51245g/blob/2fdc96a372222d6a3e47fb84263e176636a68972/mx25um51245g.c#L234

[Sanath]

Hi @Tesla DeLorean ,

 

Thank you for the information.

So, from STM32U5a9 side it supports DTR right?

Its just from the Octal Flash end we need to set the command for DDR mode

we are using ISSI Octal Flash chip BTW.

 

Regards

Sanath

[Tesla DeLorean]

So you're NOT using the STM32U5A9J-DK? Or you replaced the NOR FLASH with some unspecified ISSi chip?

On the STM32 side you need to populate the command structure with the modes of the various phases, ie command, address, data, etc.

The Macronix have distinct commands that drive the expectations in following phases.

The initialization of the interface you define clock speeds, and relationships, and the type of device,for example if it uses a Micron or Macronix type strategy. Review the component level support in the BSP, both of the U5 series, but perhaps also of H5, H7 and related platforms with broader OCTO SPI component support.

Read/review the memory part documentation, and familiarize yourself with the modes and expectations of the device.