STM32U5A9 timing issue with OCTOSPI when using both OCTOSPI1 & OCTOSPI2

[MBirk.1]

Hi,

We have a project where we use two NOR flashes connected to a STM32U5A9.

One is used for UI content, and is setup in memory mapped mode. The other is used for filesystem and is used in indirect mode.

The OCTOSPI clock is 100MHz.

UI NOR Flash, connected to OCTOSPI2: MX25L6433

FileSystem NOR flash, connected to OCTOSPI1: ISSI IS25LP256D

both flashes are connected in quad spi mode and are run in STR mode.

We have made measurements of the signals and the timings of the signals to the flash used for filesystem does not look all that good, data signal setup times were 0.6ns-0.8ns instead of >2ns. For this, the solution was to change the OCTOSPI clock used for this flash to 50Mhz.

So the clocks are as follows:
UI flash clock: 100Mhz
FileSystem flash clock: 50Mhz

I have read application note AN5050 and made a few changes according to table 8.

For both flashes:

Sample shifting: Half-Cycle
Delay hold quarter cycle: disabled

delay block: used
unit delay cell: 12
Output clock phase: 1

Now to the questions.

1. Should we not have been able to connect two NOR flashes in QUAD SPI on OCTOSPI1&2 and run them at 100MHz ? and let the IO manager manage timing ?
2. As I understand the use of delay block, it is to cope we deviation in signal timing. Will the above settings work, when running with both flashes ? (I am not tuning the values in code)

Br, Martin

[KDJEM.1]

Hello @MBirk.1,

 

What is the MCU voltage scaling range? Are you using a voltage range 1?

Are respecting the conditions mentioned in the datasheet:

The purpose of the delay block is to find the correct window that allows you to sample without having read issues and to guarantee high-performance. It's more significant in DDR mode, since the data is sampled on both edges of the clock (rising and falling) which may cause timing constraints when operating at high frequencies.

It can certainly be used with the SDR mode, but in SDR mode, we usually recommend enabling the sampling shift; The sampling is delayed by an additional half OCTOSPI clock cycle (this is done by setting the SSHIFT bit) to ensure that the data is ready at the sampling time, which allows for more relaxed input timing.

The STM32CubeMX enable the delay block with initial value of unit and phase and you need to calibrate this delay block. Two methods of calibration process utilizing the delay block are offered: Fast tuning and Exhaustive tuning.

I recommend you to take a look at How to calibrate the delay block with the OCTOSPI ... - STMicroelectronics Community.  

Please try to choose different CPU frequency and different OCTOSPI frequency when the issue is not seen:

-CPU at high frequency , OCTOSPI at low frequency with different prescalers: issue seen ?

- Reduce the CPU frequency until the issue is not seen then change the OCTOSPI prescaler (0,1,2...).

I am also interested to show the relation between the CPU frequency and the OCTOSPI frequency when the issue is not seen.

Thank you.

Kaouthar