Skip to main content
Graduate
May 23, 2025
Question

T bit confusion

  • May 23, 2025
  • 4 replies
  • 954 views

Hi,
1.As it is mentioned in CM4 user guide and also explained in tutorial, 0th bit of PC is directly loaded to T bit.And CM4 supports only thumb state ISA.To execute/decode instructions in Thumb state 0th bit of PC should be 1 which means PC should always hold address with odd numbers (i.e ODD Locations).
2.But in the attached screenshot,

Top left corner - core register window,
top right side has disassembly window,
Bottom Left-expressions window

3.Actual queries are:
3.1 why PC is holding even address(PC:0x8000654 ). And in disassembly window, address of location from where instruction needs to be executed is also even and it is matching with value in PC which is correct(Current location :0x8000654).
3.2 Once control jumps into generate_interrupt() function[Defined at location 0x80005dc] LR should hold the return address of the function,i.e, location of the next line in main.c function =>printf line(line num in main.c file :148 and disassembly window:0x8000658). So after jumping into function LR should hold 0x8000658,But as shown in snapshot, it holds 0x8000659.
3.3 After bx lr instruction associated with genreate_interrupt() function value in LR should be copied back to PC right but here value as differed by 0x01 why?Screenshot 2025-05-23 141117.pngScreenshot 2025-05-23 141211.png

    This topic has been closed for replies.

    4 replies

    Graduate II
    May 23, 2025

    The LR holds the ODD value as it indicates the type of code it's going to execute upon return.

    In the Handlers it can contain magic values like 0xFFFFFFF9 or 0xFFFFFFFD as that is a call gate that unstacks context. Either MSP or PSP

    Super User
    May 23, 2025

    > why PC is holding even address

    Because the T bit goes into the processor state bits. 

    > So after jumping into function LR should hold 0x8000658,But as shown in snapshot, it holds 0x8000659.

    Yes because LR holds not only the return address but also this bit from the status.

    >  After bx lr instruction associated with genreate_interrupt() function value in LR should be copied back to PC right but here value as differed by 0x01 why?

    And here we're again... LR bits 31..1 go into PC and bit 0 to the status. Please take your time to digest this ))

    Graduate
    May 23, 2025

    Could anyone please answer bit bit like section bus ection.I know I ahve asked many questions it that

    Graduate
    May 27, 2025

    Hi @KnarfB ,

    Please look into this issue and help me to understand this better.

     

    Best regards,

    Alex

    Graduate
    May 28, 2025

    DO you guys have link for Joseph Yiu book "The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors"

    Graduate
    May 28, 2025

    For Cortex M3 @Tesla DeLorean has shared the below link.SO I thought for M4 is also available.

    https://wiki.ifsc.edu.br/mediawiki/images/2/29/MIPM3TUG.pdf

    Graduate II
    May 28, 2025

    The MCU is materially very similar. The M4 adds a couple of instructions, and an optional single-precision FPU (M4F)

    Joseph Yiu's books are available commercially on places like Amazon, PDF's are findable if you search effectively

    Graduate
    May 29, 2025

    Thanks guys for support and quick response.@knarfb and @Tesla DeLorean .please close the ticket