THE DCMI 4 WORD FIFO IN STM3U5

[JP.4]

Hello, STM32 community,

I’m currently working with the STM32U5 and using the DCMI (Digital Camera Interface) to interface with a ADC Module which has a pixel clock and outputs 14-bit parallel data. While I understand that the DCMI supports extended data modes up to 14 bits, I wanted to clarify if the DCMI FIFO in the STM32U5 can handle the full 14-bit data width (D0–D13) in high-speed operations.

In some documentation(AN5020) and block diagrams, it appears the 4-word FIFO on dcmi might only be used for 12-bit data (D0–D11). However, for my project, I need to confirm if the FIFO can manage the additional 2 bits for 14-bit mode without causing overflow or data loss during DMA transfers.

Can anyone confirm if the STM32U5  DCMI 4 WORD FIFO fully supports 14-bit parallel data in DCMI extended data mode, or are there any limitations I should be aware of?

Thank you for your help!

Regards

JAYAPRAKASH P

AKTIS  ENGINEERING SOLUTION

[KDJEM.1]

Hello @JP.4 ;

 

Thank you for pointing out this behavior. I confirm that the block diagram figure in AN5020 is confusing and I have reported internally for clarification in the coming version.

To clarify this confusion, this figure represents an example of 12-bit.

The 4-word FIFO is implemented to adapt the data rate transfers to the AHB for 8-, 10-, 12-,14-bit data.

For more clarification please refer to RM0456 .

 

 

Thank you.

Kaouthar

[JP.4]

 Hello  KDJEM.1

 

                             THANK YOU FOR YOUR CLARIFICATION...