The DEVLNSTS[1:0] of OTG device status register seems to show a wrong logic level

[Yang Yang]

Hello, ST experts

 

STM32U595VJT6 is used on the design. The OTG part of MCU works well on USB device mode. And it functions as USB flash disk.  But when I check the logical level from OTG device status register(address offset is 0x808), there is something wrong. If the USB cable is plugged in, it is all right, DEVLNSTS[1:0] are all zero. But when the USB cable is move out, DEVLNSTS[1] is 0, DEVLNSTS[0] is 1. That means USB_D+ is 0, USB_D- is 1. But the real logical level of USB_D+ is 1(about 3.3V), USB_D- is 0.

Am I missunderstand something?

 

Best Regards

Yang

[Yang Yang]

There is a update on this thread. The DEVLNSTS[0] is occasionally logic high level when USB cable is plugged in. (The possibillity is about 2%, 50 measures, 1 logical high, 49 logical low).

[FBL]

Hi @Yang Yang 

If I understand correctly, the device is configured in Full Speed (FS) mode, and the logic state of DEVLNSTS is not deterministic. Is that correct? It is preferable to provide full configuration of USB device.

Could you attach a trace of the USB traffic? Analyzing the USB traffic trace can provide insights into the communication between the host and the device, helping us identify any anomalies or patterns that might be causing the issue. 

[Yang Yang]

Hi, @FBL 

 

The divice is configured in High Speed Mode.  Yes, the logic stat of DEVLNSTS is not deterministic. Cube MX generate the code framework as the picture below. USBX and ThreadX are used in the software.

For the USB traffic, because the probe of the oscilloscape Tektronix MSO64 is 1GHz bandwidth, there might be some distortions about the signal measured.  The USB D+ waveform showes below during transmission.

 

 

Yang

 

 

 

[Yang Yang]

Hello

 

There is another update on this thread. It is found that the read of OTG_DSTS is not done on interrupts from the device all interrupts(OTG_DAINT) reigster. Is that the key issue?

And if it is so, why the DEVLNSTS[0](USB_D-) is always logical high state when USB cable is removed.

 

BR

Yang 

[FBL]

Hi @Yang Yang 

DEVLNSTS represent logic level of DP and DM to make sure that there is a stable resume state whenever suspended. High speed levels are 0 and 400 mV. In suspend/resume the bus always goes back to full speed mode if it was in High-speed mode. So, at connection, during suspend and also leaving suspend. 

This register field is reading "logic level" which is the 3V logic level. It could be checked whenever to be sure that there is a stable resume state and not just noise that generated a system event.

[Yang Yang]

Hi, @FBL 

 

You mean DEVLNSTS[1:0] can be read not only in interrupts but also in any time during suspend?

But I don't quite understand why USB_D- is about 0V, USB_D+ is about 3.3V,  DEVLNSTS[0] is high logical level and DEVLNSTS[1] is low logical level.