Timer 1 Retriggerable One-Pulse Mode

[danielbathtub]

Hi, 

I want to do something extremely basic. 

Trigger a pulse using software for Timer 1 which is configured in Retriggerable One-Pulse Mode. 

Background: 

I can do the above if the Timer 1 is in normal One-Pulse mode. 

By simply Writing the CEN bit in TIM1->CR1. 

Now, as soon as n set me registers to the above settings I cannot generate a pulse using Software. 

I don't want to go and mess with timer settings after I've triggered a manual software pusle to "brute" force the solution. I have confirmed with my debugger that CEN is indeed set when I write the CEN bit in TIM1->CR1. The counter even starts, and all the registers are normal. To add to the confusion, If I go and plug a level signal into my trigger input of my timer 1. then in Retriggerable mode my Timer functions as expected meaning it CAN be triggered with the level signal, but NOT with software. 

Note: 

I have tried the TG bit in TIM1->EGR with no luck.

 

 Here is the evidence to my above claims: 

Here is my SMCR register contents for "Combined Reset + Triggered Mode" and TIFP1 Trigger Input

Here is my OCM4 bits, as my output is on channel 4 

Here is my CCER Registers , to enable the channel outputs

Here is my Timer 1 CR register, I am now at the point where I want to do a software pulse.  

 

Here is my timer output on the scope. Bear in mind I've got an internal Pull-Up enables.

I've got the pin in Tri-State Mode, so High will be 3.3V and Low will be ~0V. When the timer triggers, my io pin must be low. 

I've got my debug registers set to freeze timer 1 for debugging purposes. 

Look what happens now if I step over the code. 

I've got the CEN bit Set. But my output still remains at 3v3. 

Here is the output:

 

 

 

 

 

 

 

[Sarra.S]

Hello @danielbathtub, 

Looking at the screenshot of the TIM1_SMCR register; 

* SMS= 1000 corresponding to Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)

* For the TS value, TS =0x0 corresponding to internal trigger 0 (ITR0) 

Given that you want to use the "Filtered Timer Input 1 (TI1FP1)" as the trigger input, you should set the TS[4:0] bit-field to "00101" as described in the RM: 

 

[danielbathtub]

Hi @Sarra.S , 

Your response doesn't address my question, but for the sake of other I 've decided to answer to your question. 

Here is my code for the trigger selection bits. 

This is in accordance with what is in the datasheet (unless there is a mistake in the STM32Hal.h) constants. 

As you pointer out. Now I can show you the result of this. 

So we have "101" from TS_0 - TS_2 . Which is correct. 

This is the TS_3 and TS_4 bits in my debugger. 

Now, ok Ignore the TS_4 Label in the SFR's and the other stuff I'm gonna show you what the manual says and you will see that my register corresponds exactly to what I want, meaning there is no mistakes. 

See the Yellow is what I showed you in the first picture of my registers and the Orange is the second picture I showed you of my registers. 

 

Regards, 

 

 

[waclawek.jan]

There is no native mechanism through which a trigger can be forced in a timer, so you have to generate a real trigger. One way to do this may be to switch TS to one of the ITRx (e.g. an unused timer) and generate trigger from there (e.g. by setting that timer's TIMx_CR2.MMS to Update and generating Update by setting TIMx_EGR.UG).

JW

 

[danielbathtub]

Hi Jan, 

Thank you. Is this only true for when the Timer is in retriggerable One-Pulse Mode ?