Skip to main content
Visitor II
February 7, 2025
Solved

TXE interrupt comes even though TXEIE is not enabled

  • February 7, 2025
  • 4 replies
  • 1167 views

Basic setting of USART2: DMA Transfer and receive via interrupt as RS485.

As long as only DMA transfer is ongoing, all will be ok. At first time a receive interrupt will occur, the transmit will trigger an interrupt, even though no TXEIE is set. This crashes the system 

The same settings for UART5 and USART3: there it works fine without problems (RS232 or RS485).

Whats going wrong, or some errata for this behavior?

MCU type: STM32F756

    This topic has been closed for replies.
    Best answer by rodi66

    I got a very simple solution, but i do not understand this, why it works at the other U(S)ARTS well:

    I enabled TE and UE in CR1 register at the same time in this way:

    USARTx->CR1 |= (CR1_TE | CR1_UE);

    -->  USART2 works differently to USART3 and UART5

     

    So the handling of the control register 1 was little bit wrong, but had no influence to USART3 and UART5 but on USASRT2. murphy jokes ;-).

    All U(S)ARTS work in the same (fine) way; the reference manual describes the handling in this way...

    USARTx->CR1 |= CR1_TE;
    USARTx->CR1 |= CR1-UE;

     

    Thanks for your tips.

    4 replies

    Super User
    February 8, 2025

    DMA Transfer and receive via interrupt

    If you use the "HAL" library, it can be "peculiar behavior" of the library. Do not let the system crash. Handle the interrupt and dismiss it.

     

    Graduate
    February 8, 2025

    Your own code or HAL?

    The common mistake in UART interrupt handler is checking for TXE flag without checking for TXEIE. Both should be set to execute the TXE handler path.

    rodi66Author
    Visitor II
    February 10, 2025

    That ist not the case: i check the flags proper. After setting the CR1 Bits in a little different way, the sytem works fine. Unfortunately, setting brakepoint s in the interrupt handler also led to confusion in the ISR bits.

    ST Employee
    February 10, 2025

    Hi @rodi66 

    What makes you think the source for the unexpected interrupt is TXE ? is it because TXE flag is 1 in ISR ?

    By the way, at end of transmission, TXE will stay at 1 and cannot be cleared in ICR, but this should not trigger USART2 interrupt.

    What is USART2 ISR register content when this unexpected interrupt occurs ?
    Regards

    rodi66Author
    Visitor II
    February 10, 2025

    The TXE bit was set and the TC Bit was cleared. But no TXEIE or TXIE bit is set in the CR1 register.

    Super User
    February 10, 2025

    This is OK. TXE indicates that the transmit buffer register USART_TDR is empty (all bits shifted out). It can be empty even when TXEIE is not set.

     

    rodi66AuthorAnswer
    Visitor II
    February 11, 2025

    I got a very simple solution, but i do not understand this, why it works at the other U(S)ARTS well:

    I enabled TE and UE in CR1 register at the same time in this way:

    USARTx->CR1 |= (CR1_TE | CR1_UE);

    -->  USART2 works differently to USART3 and UART5

     

    So the handling of the control register 1 was little bit wrong, but had no influence to USART3 and UART5 but on USASRT2. murphy jokes ;-).

    All U(S)ARTS work in the same (fine) way; the reference manual describes the handling in this way...

    USARTx->CR1 |= CR1_TE;
    USARTx->CR1 |= CR1-UE;

     

    Thanks for your tips.