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AMacd.1
Graduate II
February 4, 2025
Solved

What are the Memory Addresses for SRAM1 and SRAM2 on STM32U0

  • February 4, 2025
  • 3 replies
  • 1090 views

The Reference Manual for STM32U0 series MCUs, RM0503 Rev2, specifies, in table 2 on page 57, that SRAM starts at 0x2000 0000 and ends at 0x2002 9FFF.  This is a contiguous region with a size of 168KB.  However, the Size column shows 40KB.  This document is confusing.  What is the correct size of SRAM?

Furthermore, in section 2.3 on page 60,  table 5 lists 2  SRAM segments, SRAM1 (32KB) and SRAM2 (8KB).  These add up to 40KB, which is the size listed in table 2.  However, the locations of these segments within the SRAM region are not documented.  The table does not specify where the start addresses are, nor does it specify whether or not the two segments are contiguous or separated.

What are the start addresses of SRAM1 and SRAM2?

Why are they separated?

What are the differences between these two segments?

Is  there a different document that explains these in better detail?

    This topic has been closed for replies.
    Best answer by KnarfB

     Some info is in the data sheet, like for  STM32U073x8/B/C ( DS14548 - Rev 2):

    "

    • SRAM1: 32 Kbytes with hardware parity check, mapped at address 0x2000 0000
    • SRAM2: 8 Kbytes with hardware parity check, located at address 0x1000 0000
    SRAM2 is also mapped at address 0x2000 8000, offering a contiguous address space with SRAM1
    (8 Kbytes aliased by bit band).

    The content of SRAM2 is retained in Standby mode.
    It is write-protected with a 1-Kbyte granularity.

    "

    No idea about "bit band" here, afaik, Cortex-M0+ does not support bit banding.

     

    The "STM32U0 Series presentation" STM32U0 Online Training - STMicroelectronics mentions:

    "

    40 KB of SRAM split into two separate memory ports
    enabling concurrent accesses: 32 KB for SRAM1 and 8
    KB for SRAM2

    "

    So, you may place some code in SRAM1 and data in SRAM2 for parallel DMA data transfers and CPU instruction fetching.

    Or In Standby mode with SRAM2 content preserved

    hth

    KnarfB

    3 replies

    A
    AA1
    Visitor II
    February 4, 2025

    This and other issues are here: Missing section IRTIM in STM32U0 RM and more. I think the correct RAM addresses are also there. A new RM version with the issues fixed should already be available.

     

    S
    STTwo-32
    Technical Moderator
    February 4, 2025

    Hello @AMacd.1 @AA1 

    I will see if this is already reporter or not and I will escalate it for correction on the next revision if it has to. Thanks for both of you.

    Best Regards.

    STTwo-32

    K
    KnarfBAnswer
    Super User
    February 4, 2025

     Some info is in the data sheet, like for  STM32U073x8/B/C ( DS14548 - Rev 2):

    "

    • SRAM1: 32 Kbytes with hardware parity check, mapped at address 0x2000 0000
    • SRAM2: 8 Kbytes with hardware parity check, located at address 0x1000 0000
    SRAM2 is also mapped at address 0x2000 8000, offering a contiguous address space with SRAM1
    (8 Kbytes aliased by bit band).

    The content of SRAM2 is retained in Standby mode.
    It is write-protected with a 1-Kbyte granularity.

    "

    No idea about "bit band" here, afaik, Cortex-M0+ does not support bit banding.

     

    The "STM32U0 Series presentation" STM32U0 Online Training - STMicroelectronics mentions:

    "

    40 KB of SRAM split into two separate memory ports
    enabling concurrent accesses: 32 KB for SRAM1 and 8
    KB for SRAM2

    "

    So, you may place some code in SRAM1 and data in SRAM2 for parallel DMA data transfers and CPU instruction fetching.

    Or In Standby mode with SRAM2 content preserved

    hth

    KnarfB

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