what do they mean by UART multibuffer communication?

[RSolo.1]

Tell me about multibuffer communication in the registers of the UART. We have a description of the RXNE flag. "The RXNE flag can also be cleared by writing a zero to it. This clearing sequence is recommended only for multibuffer communication". It turns out that when using DMA, you can reset RXNE this way. But why? After all, DMA does this automatically during operation.

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Edited to add 'F4' and 'DMA' Labels.

[Andrew Neil]

Which document are you referring to?

A screenshot with context would help ...

[RSolo.1]

this is from the reference manual:
Bit 5 RXNE: Read data register not empty
This bit is set by hardware when the content of the RDR shift register has been transferred
to the USART_DR register. An interrupt is generated if RXNEIE=1 in the USART_CR1
register. It is cleared by a read to the USART_DR register. The RXNE flag can also be
cleared by writing a zero to it. This clearing sequence is recommended only for multibuffer
communication.
0: Data is not received
1: Received data is ready to be read.

[Andrew Neil]

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@RSolo.1 wrote:

this is from the reference manual:

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What Reference Manual?

You haven't given a part number!

How to write your question to maximize your chances to find a solution.

 

[RSolo.1]

I beg your pardon. Here is the document. RM0090

[Tesla DeLorean]

Identify the part you're talking about, ST makes literally hundreds of different STM32 parts.

Multi-Processor mode is a 9-bit comms mode using a bit to Identify command/data in other 8-bits.

Some parts have FIFO of varying depths for some UART

[RSolo.1]

I'm not talking about multi-processor. I speak for multibuffer communication. 
as I understand it, in this mode in DMA two address spaces are used: DMA stream x memory 0 address register and DMA stream x memory 1 address register.
otherwise it is called Double buffer mode

[Andrew Neil]

So this?

https://www.st.com/resource/en/reference_manual/dm00031020-stm32f405-415-stm32f407-417-stm32f427-437-and-stm32f429-439-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf#page=977

[RSolo.1]

yes, that's it. I just don't understand in what situation it might be necessary to do this: The RXNE flag can also be cleared by writing a zero to it.

[Andrew Neil]

As it says,

"The RXNE bit must be cleared before the end of the reception of the next character to avoid an overrun error"

(my emphasis)

So it's just informing you that, in the multibuffer case, the DMA does take care of it - so you don't have to ?

 

PS:

To the question in the title, "what do they mean by UART multibuffer communication?" I agree that the term "multibuffer" is never actually defined  in the document!

Does it just mean, "any transfer using DMA"?

 

 

[RSolo.1]

I understand, thank you. They just confused me with their text. I already thought that in some cases it needs to be done manually

[Andrew Neil]

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@RSolo.1 wrote:

I already thought that in some cases it needs to be done manually

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Indeed it does.