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July 27, 2024
Question

what is the cause of this hardfault ?

  • July 27, 2024
  • 2 replies
  • 971 views

I execute my program on unmodified nucleo-u5a5zj-q , it reliably reach the "Default_Handler" from the default startup_STM32U5A5ZJTXQ.s.

Screenshot from 2024-07-27 22-54-07.png

My understanding from the screenshot:

  1. It goes here because a hardfault occurs:
    1. SHCSR_S.HARDFAULTACT = 1
    2. HFSR_S.FORCED = 1 --> not sure about the meaning of that one
  2. This hardfault is a "bus error":
    1. BFSR_S.PRECISERR=1
    2. BFSR_S.BFARVALID=1
    3. MMFSR_S = 0
    4. UFSR_S = 0
  3. The faulty instruction is execution from flash (ldrd at 0x0802fb1a): info from CALL STACK view
  4. The "bus error" is therefore caused by a 64 bit read at 0x2066fe88:
    1. BFAR_S = 0x2066fe88
  5. 0x2066fe88 is in the Main RAM, well inside the current stack, so the hard fault should not occur

One or more points above may be wrong since the conclusion makes no sense

Notes:

  1. I wrote "may be" rather than "is" because the exact same binary works just fine on other boards!
  2. I tried reflashing the board (--erase all --download)
  3. I use the internal 48MHz oscillator and the failure happens even with 15 wait states (FLASH_ACR.LATENCY=0xF)
  4. Cache is disabled
  5. All peripherals / CPU features except the list below are in their default state:
    1. RCC
    2. GPIOs
    3. USART1
    4. USART2
    5. TRNG
    6. FLASH (latency)
    7. CoreDebug / DWT (used in an attempt to count CPU cycles)
    This topic has been closed for replies.

    2 replies

    Graduate II
    July 27, 2024

    LDRD/STRD are sensitive to alignment issues for the pointers

    If a random interrupt, perhaps check source via NVIC

    Check VCAP voltage and capacitors, these can cause sensitivity and failure issues. Certainly seen FLASH issues with insufficient bulk capacitance.

    https://github.com/cturvey/RandomNinjaChef/blob/main/KeilHardFault.c

    acapolaAuthor
    Explorer
    July 28, 2024

    Thanks for your feedback.

    The address of the faulty address seems well aligned isn't it ?

    • base register is r3, which is aligned mod 8: 0x2066fe68
    • offset is 32, so final address (0x2066fe88) is also aligned mod 8

    I believe that if the fault was due to an interrupt, the fault status registers would point to the interrupt code. Anyway my code do not have interrupt so I disabled them by setting PRIMASK=1, the same hardfault still occurs.

     

    The STM32_Programmer_CLI tool indicates 3.29V, that seems well within the specs (I use brand new, unmodified nucleo board). I searched for "VCAP" in the nucleo doc but did not find it. Is there anything else I could check ?