Skip to main content
damien1
Associate II
April 24, 2023
Solved

Is there an example of how to perform DDR data bit swapping as described in AN5122?

  • April 24, 2023
  • 1 reply
  • 1881 views

We are using LPDDR2 and have wired the data bits as per the ST provided example STM32MP15XXAD_LPDDR2x16-Example-A01_Schematic.PDF (attached)

We have swapped the same bits in the DQ15:8 byte as per the PDF but I can't find anything to tell me how to perform this swapping in the devicetree or otherwise.

Below is the screenshot from the Application Note detailing that bit swapping is possible.
_legacyfs_online_stmicro_images_0693W00000bifUDQAY.png

This topic has been closed for replies.
Best answer by PatrickF

Hi @damien1​ ,

on a pure RAM, no matter the data bus swapping (bits within a byte or bytes Vs bytes), your read what your have written. So, no need to configure any HW/SW about this.

Obviously, in case of bytes swap, DQS/DQM should follow their byte.

There is anyway some restriction on byte and but swapping (e.g. D0-D7 on LPDDR2/3 should be on byte0 without any bit swap) as data bus could also carry access to memory internal config/status registers.

On DDR3/DDR3L, all data swaps are allowed because writting memory register is done using address bus as data (which is not the case on LPDDR).

Regards,

In order to give better visibility on the answered topics, please click on 'Select as Best' on the reply which solved your issue or answered your question. See also 'Best Answers'

1 reply

PatrickF
PatrickFBest answer
Technical Moderator
April 25, 2023

Hi @damien1​ ,

on a pure RAM, no matter the data bus swapping (bits within a byte or bytes Vs bytes), your read what your have written. So, no need to configure any HW/SW about this.

Obviously, in case of bytes swap, DQS/DQM should follow their byte.

There is anyway some restriction on byte and but swapping (e.g. D0-D7 on LPDDR2/3 should be on byte0 without any bit swap) as data bus could also carry access to memory internal config/status registers.

On DDR3/DDR3L, all data swaps are allowed because writting memory register is done using address bus as data (which is not the case on LPDDR).

Regards,

In order to give better visibility on the answered topics, please click on 'Select as Best' on the reply which solved your issue or answered your question. See also 'Best Answers'

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.NEW ! Sidekick STM32 AI agent, see here