Hi @damien1 ,
on a pure RAM, no matter the data bus swapping (bits within a byte or bytes Vs bytes), your read what your have written. So, no need to configure any HW/SW about this.
Obviously, in case of bytes swap, DQS/DQM should follow their byte.
There is anyway some restriction on byte and but swapping (e.g. D0-D7 on LPDDR2/3 should be on byte0 without any bit swap) as data bus could also carry access to memory internal config/status registers.
On DDR3/DDR3L, all data swaps are allowed because writting memory register is done using address bus as data (which is not the case on LPDDR).
Regards,
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