STM32 MCUs Products

I am currently working on the STM32H7S78-DK board & after building GPIO demo present Example code from git repository of that STM32 provided, while flashing binary from the STM32 programmer I faced issue it is mentioned belowWhen code is flashed from STMcube programmer it sometimes flashed and sometimes showing error that , core is locked or core is under resetWhen code flashed successfully , I did not get expected result (Ex. LEDs not blinking)Can you please help me to resolve this error, I attached screen shots of errors below  

Hello, we use STM32F413RGT6 as slave board communicate through rs485 bus. In application, we drive rts by emulated gpio. We use for update of the board HW uart bootloader. Due to weakness of the HW bootloader we face some problems during update on half duplex uart, because HW bootloader sometimes response sooner, than is complete msg send. Due to it we receive damaged ack, for example 0xb9 instead of correct 0x79. Next challenge was activate uart HW bootloader, because STM logic is, that first activity on any digital bus lead to choose that bus as update bus, so we must rework our application to have stable start until we start to communicate on update uart (rs485) bus. This could be improved forexample by HW boot pins... Last thing, what i can say as improvement could be better specification in an2606-stm32-microcontroller-system-memory-boot-mode-stmicroelectronics.Because if you want to jump from bootloader to the application, you must send sequence init, GO command and ju

Hi all,I'm trying to find out if any STM32 MCUs support hardware input qualification on GPIOs, similar to what's available on TI C2000 MCUs.On the C2000 series, GPIOs can be configured for input qualification using a sampling window—typically 3 or 6 samples spaced apart based on the system clock. Here's a reference from the C2000 TRM for clarity (see attached images):Sampling is done every 2 × QUALPRD × T_SYSCLKOUTThe input must be stable for multiple consecutive samples before it's considered validThis helps filter out glitches or noise on input lines without software debounceI'd like to know:Do any STM32 series (F0/F1/F4/G4/H7, etc.) provide similar hardware input qualification or multi-sample filtering at the GPIO input level?If not at the GPIO level, do any EXTI lines or timer input capture channels offer configurable digital filtering that could replicate this functionality?Are there STM32 families with 'majority-vote' digital filters like what some comparators or HRTIM inputs pro

Hi, I have configured my STM32H563AI CubeMX-project to use "JTAG with Trace  Synchro(4bits)" and assigned the corresponding pins. Also, I explicitly activated the corresponding registers in DBGMCU and DCB by adding: SET_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN); SET_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN); SET_BIT(DCB->DEMCR, DCB_DEMCR_TRCENA_Msk);to MX_GPIO_Init. However, when I try to trace using Ozone V3.38g I always get a "No trace clock present, trace may not work correctly."-warning and nothing is read out from the instruction cache. My trace settings in Ozone are: Trace Source: Trace PinsCPU Frequency: 250 MHzTrace Port width: 4 bitMaximum Instruction Count: 100M I used an oscilloscope to look at the TRACECK-signal but found nothing there, it only ever has 0V. Also, I verified my tracing setup, using a SEGGER Cortex M-Trace Reference Board and with this it was just working fine. Also, I verified, that the corresponding registers

What is the process to use the ADC on STM32L152rct6 to wake up the micro from Sleep?

Hey everyone,I'm currently working with the STM32H7S78-DK.I'm trying to set up an external memory loader project, executing code from external memory with XIP, while also partitioning out the SDRAM in a few different addressable chunks in the memory layout tool.But, it seems when I set this up in CubeMX, I'm not able to configure the project in a way where I can partition out the SDRAM by address in the memory configuration page, and also use the external memory loader.This is based off of attempts to modify the XIP template IOC file.What's the best way to configure this? Or is it possible with the external memory manager?Also, if there are resources to help deepen my admittedly shallow understanding of the External memory loader / manager middleware, and bootloader system for the STM32H7? I've found this tutorial:https://wiki.st.com/stm32mcu/wiki/Getting_started_with_External_memory_Manager_and_External_memory_loaderBut I'd love a more datasheet style document to outline all the memor

Hi,while I'm configuring the FMC interface i come cross this memory map and i couldn't understand it. Does the FMC SDRAM Bank 1 have 4 possible regions? if yes, does SDRAM Bank 2 have the same option.what about the External Memory region, are those for SRAMs and External Device for SDRAM?those kinds of questions come to my mind, if someone could help me with.most important question, I want to use SDRAM bank 1 (SDCKE 0 will be enabled) and SRAM1 (NE1 will be enabled), is this possible?i believe i have read this somewhere that it could be done, but not sure, also, is there some sort of limitation of both can be enabled together or i should use SDRAM bank 2 and one of the SRam banks and that will be more reliable and efficient?Thank you and best regards

I am confused about which clock(s) drive the timers.  In the reference manual is says the APB clock drives the timers but there are 5 APB clocks.  Also, in STM32CubeMX there is a "Timer Group Clocks".  What clocks drive which timers or is the one drives all (Timer Group Clocks)? 

I have questions on the System Memory Boot Mode of the STM32G070CB MCUSetup:Access the System Memory Bootloader Mode every power cycle. Hence, I updated the Option Bytes as below:The MCU contains the Application image only; it does not contain a custom bootloader.Using Cube Programmer, configure the nBoot0 option bytes, able to run as System Memory Boot Mode OR Main ApplicationWhat I tried to do was exit the System Memory Boot Mode and Access the Main Application, but failed:Tried using the UART sending the GO Command with the Application Address 0x0800 0000, but the MCU does not work (no UART Log) Tried using the UART method to send the GO Command with the Application Address stored in the Image like below, the MCU does not work. Tried to uncomment the “USER_VECT_TAB_ADDRESS” in system_stm32g0xx.c.The MCU outputs some unexpected UART log if sending the GO Command with the Application Address 0x0800 0000            &

I am trying to detect both rising and falling edges on a GPIO input using EXTI.I am using a STM32H755 (144 pin) - SYSCLK is 400MHz, but I am using the CM4 core, so the CPU clock is 200MHz. APB Timer clock is also 200MHz.The signal I am monitoring is coupled through an opto-isolator, and having scoped it, seems to have a rise-time of approx. 5us. I am wondering if this is too slow for EXTI rising / falling edge detection?I've been looking at both the datasheet and reference guide for the STM32H755 and I could not find any data on max and min rise times for edge detection to function reliably.

How to unbrick a C0 if user firmware reprograms SWD pins as IO? Because by default BOOT0 pin is disabled so there's no way to enter the bootloader unless it's enabled in OPTIONS bytes. I've added a failsafe 2 second delay at bootup before running any GPIO config, but I'm curious if there's any other way to unbrick. Or if RDP1 is enabled, how to change it back to RDP0 if you can't get in via SWD or into bootloader because BOOT0 isn't enabled? Or am I missing something?BOOT0 pin by default is disabled in OPTION bytes, but you can't enable it, or erase the firmware/flash if SWD is not working...I'm using STM32C071 but I assume it's all C0 if they don't have the BOOT0 pin enabled by default.

Whether the two buses can be used at the same time？ Winbond's SDRAM is used to find a high probability of reading and writing errors in SDRAM data。 but there is no problem with using ISSI. If you don't read or write to the external SRAM, it's fine。

I have compared my platforms using PDM microphones related to PDM to PCM and filtering:Platform 1:STM32H747 (Portenta H7), with SW PDM2PCM filter (and optional to add post-processing)Platform 2:STM32U5A5 with ADF filter (in MCU) or external PCMD3180 chip.My favorites:STM32U5A5 with ADF: but unfortunately just mono MICPCMD3180: still room for improvements, e.g. using "channel summing" for +6dB SNR or tweaking the filtercoefficientsIn general: all filters are pretty similar. The major differences are on:the DC offset they have left (STM32U5A ADF needs for sure a HP filter)the harmonics created (distortion): just with a post-filter (e.g. on PDM2PCM) I could improvethe noise in high frequency spectrum (above 10KHz): STM32U5A5 ADF is the winner hereHere the result comparison (should be an animated GIF to see the differences):So, my conclusion: if I need a PDM MIC - use the STM32U5A5 ADF (if just one MIC needed), otherwise use external chip (PCMD3180).

I bought few STM32C071G8U6N from Mouser few month ago.As I know, the SRAM size in spec is 24K, but I will get error message as below when ZI-data over 8KB"Error: L6406E: No space in execution regions with .ANY selector matching xxx.o(.bss)."Program Size: Code=33736 RO-data=360 RW-data=132 ZI-data=6724 And the data in iirDataQueue will change into 8192 or around 65535 unexpected.. Following is my code(work fine on other platform), (iirData is no error).  memmove((uint16_t*)&dspMem.iirDataQueue[0], uint16_t*)&dspMem.iirDataQueue[1], (ADC_DATA_QUEUE_LEN - 1) * sizeof(dspMem.iirDataQueue[0])); dspMem.iirDataQueue[ADC_DATA_QUEUE_LEN - 1] = dspMem.iirData; We have also been using other series of products for a long time, such as STM32L4, but none of them is as frustrating as STM32C071. Could you please provide me with some direction to debug? Thanks.Environment:CubeMx 6.15.0 + STM32C0 1.4.0Keil MDK-ARM 5.29.0.0STM32C0xx_DFP 2.2.0 

Hello, I have a project to measure the frequency (10Mhz) on an PA5 input and PWM output on PA6, with the counting triggered on PA0 (1PPS), CPU STM32F411, my problem is that the value TIM2 is always wrong, I must have around 10Mhz, I think that the configuration of my Timer 2 is not good but I don't see where the problem is.File attached.Best regards.Sébastien..

Hello All, @TDK, @STTwo-32, @Peter BENSCH I am using STM32F407G-DISC1 with SN65HVD230 CAN Board Network Transceiver Evaluation Development Module connected to PCAN.Connections are as followsSTM32F EVK pin PD0(CAN1_RX) to Rx of SN65HVD230 STM32F EVK pin PD1(CAN1_TX) to Tx of SN65HVD230 3V and GND is connected as well.SN65HVD230 CANH to Pin 7 (DB9 of PCAN)SN65HVD230 CANL to Pin 2 (DB9 of PCAN)Common GND connected as well (Pin 3 DB9 of PCAN) to EVK GND.I have a script to transmit and receive message from the EVK, speed is set to 1 Mbps, i am able to transmit data from EVK to PCAN and the same is displayed in PCAN View. But the problem i am facing is i am not able to receive any data sent by PCAN to EVK.I am trying to send a Standard CAN message, no Extended frame, no RTR, just 0x7FF(ID), DLC - 8, Data 01 02 03 04 05 06 07 08 cycle time is 50mS. And the same filters are set for Rx Mailbox in my script.Please let me know any suggestions or if i am mis

There are two situations where I'm unclear on how CAN filters would behave. 1. Direct ConflictOne filter says reject 0x0 to 0x123One filter says send 0x0 to 0x123 to FIFO0 2. Different behaviour for a subset of messagesOne filter says send 0x0 to 0x123 to FIFO0One filter says send 0x0 to 0x012 to FIFO1 Is there a filter priority, or is this undefined behaviour? I assume this depends on the CAN controller, so in my case I'm using the STM32G474, but I'm curious if most controllers have similar behaviour here.

Hi everyone,I'm using the NUCLEO-H755ZI-Q board and I’m a bit confused about its Ethernet support.The user manual (MB1363 Rev C) shows that both H745ZI-Q and H755ZI-Q support Ethernet using the LAN8742A PHY. It also lists jumpers and solder bridge settings for enabling RMII.But when I checked my H755ZI-Q board, it looks like the PHY chip and RJ45 connector are not soldered. So now I’m not sure:Does the H755ZI-Q actually support Ethernet out of the box?Or is Ethernet only available on the H745ZI-Q version?Would appreciate any help or clarification. Thanks!

Can we use STM32N series high end crypto version in medical devices? Currently we are using H series from ST but we are facing some issue in CPU utilization and speed. Apart from external flash is there any major difference where N series is lagging with respect to H series part?? Is there any limitation to use N series in MATLAB?? Any limitation to us Link for n serieshttps://www.st.com/en/microcontrollers-microprocessors/stm32n657x0.html  Br,DJ

Hi All, Using STM32CubeProgrammer with the ST-LINK in SWD mode.If the RDP flag is set to 0xBB (level 1) and programmed the programmer can no longer connect to the device.How can I reconnect to the device to set it back to 0xAA? _Carl_

Hello ST,The STM32N6 Datasheet (DS14791 Rev 2) claims that the device has 1 HR Timer and 4x 32-bit General Purpose Timers, yet the Functional Overview section does not support these claims.  Nor does the Reference Manual (RM0486 Rev 1).  Could you please cdis-ambiguate for us, and mark the incorrect documentation for revision?Also, is it really true that the DP-FPU capability is not present:-(Thank you!Regards,Dave

Hi,I am trying lock a portion of Flash memory using WRP(Write Protection). when I am configuring the Option bytes for WRP. I am using STM32L443VC MCU and I have multiple questions:1. Which area to select WRPAreaA or WRPAreaB for page 0 to page 11 because there is no division of area given?2. I am trying to lock from page 0 to page 11 in the flash memory but I am seeing different values even after OBL launch:example: WRPStartOffset = 0x80  (Expected: 0x00)                WRPEndoffset = 0x0B (Expected: 0x0B)This is because in the reference manual I see FLASH_WRP1AR reset value is 0xFFXX FFXX and in the register value is 0xFF00 FFFF. If I use Register value got 0xFF0B FF80 instead of 0xFF0B FF00. if I assume 0xFF00 FF00 i am getting 0xFF0BFF00. Even I tried for different page offset still I am seeing Startoffset value different. Please check the attached snapshots for your reference.3. I am using segger jlink to flash the code and Please l

Hello everyone,I'm observing inconsistent FLASH ACR EMPTY flag behavior on two STM32G070RB chips (DEV_ID 0x6460) after a full chip erase by using STM32CubeProgrammer]Observed behavior:STM32G070RB (REV_ID 0x2000): After full erase, FLASH_ACR EMPTY flag correctly sets to '1' (chip boots into system memory). This is the expected behavior.STM32G070RB (REV_ID 0x2001): After full erase, FLASH_ACR EMPTY flag remains '0'. The chip attempts to boot from main Flash (0x08000000) despite being empty, leading to unexpected behavior.Questions: Is there a documented difference in the Flash empty check mechanism or FLASH_ACR EMPTY flag behavior between STM32G070RB REV_ID 0x2000 and REV_ID 0x2001?Are specific option byte settings or erase sequences required for REV_ID 0x2001 to correctly assert the EMPTY flag after a full erase? (I have tried power cycling.)Thanks,Tomislav

Hello All,I am very worried about this as time is short.I am attempting to get my STM32L073RZ into low power mode using STM32CubeIDE version 19, and it wakes as soon as it sleeps. I am wondering if this is a problem with my code, or possibly an issue with the STM32CubeIDE?I am attempting sleep mode like so:void Enter_Stop_Mode(void) { ConsolePrintf("Preparing to enter Stop mode\r\n"); // Clear Wake-Up flag __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hrtc, RTC_FLAG_WUTF); ConsolePrintf("RTC Wake-Up flag cleared\r\n"); // Enter Stop mode (low-power mode) ConsolePrintf("Entering Stop mode\r\n"); HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); ConsolePrintf("Exited Stop mode\r\n"); } And this fails. Am I the only one experiancing this, how have others got this working?Are there any examples I could go off of?For more context, here is my repo: https://github.com/CropWatchDevelopment/tempSensorx2If anyone could help, I would be very greatful.-Kevin

Hi everyone,I'm developing a bare-metal application with an STM32H725RG MCU using STM32CubeIDE (including HAL and code generation).I want to use the IWDG1 for reliability purposes, but for some reason, it seems to not work for me at all - upon startup, the MCU enters the Error_Handler loop, due to the HAL_IWDG_Init call returning HAL_TIMEOUT.In particular, I enabled the IWDG1 in the .ioc file editor, so it gets initialized and enabled by the generated HAL code. This enables the LSI as expected (RCC_CSR = 0x3), and I can confirm that the LSI itself works by outputting it to the RCC_MCO_2 pin.However, the initialization of the IWDG doesn't seem to complete. As far as I can tell from debugging, all the initial writes to IWDG_KR work as expected, and IWDG_PR and IWDG_RLR receive their correct values. This results in IWDG_SR = 0x3 as expected, which should go back to 0x0 within a few LSI cycles as the changes are applied - but this never happens. Instead, IWDG_SR remains at 0x3 permanently,