STM32 MCUs Products

Hello,Using RS485 for modbus communication.It is observed that, if we disable STOP2 mode then RS485 communication works fine (no frame loss). but asa we keep STOP2 mode then at the time of wakeup I found some frame loss.#define RS485_TX_ENABLE() HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_SET) #define RS485_RX_ENABLE() HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_RESET) static void MX_LPUART1_UART_Init(void) { hlpuart1.Instance = LPUART1; hlpuart1.Init.BaudRate = 115200; hlpuart1.Init.WordLength = UART_WORDLENGTH_8B; hlpuart1.Init.StopBits = UART_STOPBITS_1; hlpuart1.Init.Parity = UART_PARITY_NONE; hlpuart1.Init.Mode = UART_MODE_TX_RX; hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; if (HAL_RS485Ex_Init(&hlpuart1, UART_DE_POLARITY_HIGH, 0, 0) != HAL_OK) { Error_Handler(); } if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOL

Hello everyone,I'm currently working on a UART communication protocol using STM32 USART in multiprocessor mode (MME / Address Mark) over RS485. My goal is to receive variable-length data frames only when the address matches, and use DMA + IDLE interrupt to detect the end of each frame.:wrench:Frame format:- First byte: 9-bit address word (MSB = 1)- Followed by N data words (9-bit, MSB = 0):white_heavy_check_mark:Setup:- USART configured in 9-bit data mode (no parity)- MME (multiprocessor mode) enabled- Address match set via ADD[7:0]- DMA reception via `HAL_UARTEx_ReceiveToIdle_DMA(...)`- `__HAL_UART_ENABLE_IT(&huart, UART_IT_IDLE)` enabled- IDLE handling expected in `HAL_UARTEx_RxEventCallback()`:cross_mark:Issue:- When MME is **disabled**, IDLE interrupt works correctly, and the RxEventCallback is triggered on frame end.- When MME is **enabled**, the USART correctly detects the address and wakes up from mute mode, and DMA begins receiving data.- But **IDLE interrupt never triggers

I am verifying USB implementation using Nucleo-H7S3L8.When I executed CDC_Standalone in STM32CubeH7RS using the Debug button and ran the Appli code, the function “HAL_PWREx_EnableUSBVoltageDetector()” in ‘MX_USBPD_Init()’ did not return HAL_OK and an error occurred.Within this function, the “USB regulator ready flag (PWR_CSR2_USB33RDY)” is not set, causing a timeout and resulting in a HAL_ERROR.However, when I stop debugging, disconnect the USB cable, and reconnect it, the COM port appears in the Windows Device Manager.I have not made any changes to the contents of CDC_Standalone.The jumper on JP3 on the board has been changed from STLINK to UCPD.What should I do to properly debug USB on this board? 

Previously had issues with TXP flag never clearing for interrupt-driven SPI.  Changed some HAL code and got it to work.Moving on the DMA, the first 8 bytes received match the transmit buffer and the 9th byte matches a byte farther into the transmit buffer.I suspect that the entire DMA buffer is transmitted at the start filling the transmit FIFO and bytes are dropped until the FIFO gains an empty slot and data can once again enter the FIFO.  This seems consistent with the TXP flag not properly clearing when the transmit FIFO is full.   Can anyone tell me what makes the TXP flag not operate?  

I have done a PCB Design with microcontroller STM32L071CZT6 as the mcu. PB15 which is a 5V tolerant pin is connected to a source of 4.9 V with a resistor 270 kOhm in between. I measured the voltage at the PB15 pin to be 4.9 V but, when I set it as Digital Input pin with no pull it does not read HIGH. But, I remember the previous batch of boards with the same design had this pin read HIGH by the same firmware.

Hello, I am trying to write some non-blocking motor driver code for a STM32F401Re board. Currently, I am setting the timers to PWM mode and adjusting the ARR to change the PWM frequency using an IRQ handler. This approach is working for TIM3 output, but TIM2 seems to stop outputting after one iteration of the while loop. I've been through the registers and it looks like the CC1IF isn't always being set for TIM2 and I'm not sure why. By adjusting the ARR, shouldn't both timers roll-over after hitting their new max value? I've attached the main file and the A4988 driver file I'm writing. For the A4988 file, the methods in question are A4988_run() and A4988_IRQ_Handler().   Thanks!    

Hi,I'm currently debugging what I think to be a code issue. I have a custom board with all peripherals physically disconnected and a NUCLEO-U575ZI-Q dev kit. The lowest current I see is about 250uA on both setups, with a sawtooth charge/discharge waveform from what I think is the internal switching regulator (consistent when using other stop mode functions). I've implemented a few examples for entering stop mode, and review any application notes I could find for how to handle it. Stop1 and Stop2 both yield current in the ~200uA range, and Stop3 yields about 35uA. The only way I have found to decrease the current the most were changing the "PWR_CR1_LPMS_X" parameters in the HAL_PWREx_EnterSTOP1Mode function:Original: MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_0);New 1: MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_1); -> Gave me <200uA on my custom boardNew 2: MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_2); -> Gave me 90uA on my custom boardChangin

Hello everyone,I'm facing a HardFault issue when jumping from a bootloader to an application on the STM32L476RG.The fault occurs right at the beginning of the application, specifically at the instruction bl __libc_init_array inside the Reset_Handler (from startup_stm32l476xx.s).Memory layout:Bootloader: starts at 0x08000000, size: 12 kBApplication: starts at 0x08004000, max size: 150 kB (currently using ~95%)RAM usage: around 30%Bootloader jump sequence:typedef void (*p_function)(void);static void app_start(boot_t *self) {HAL_DeInit();self->boot.address = *(volatile uint32_t *)(self->address.app + 4);self->boot.jump_to_app = (p_function) self->boot.address;__set_MSP(*(volatile uint32_t *) self->address.app);SCB->VTOR = self->address.app;self->boot.jump_to_app();}Here, self->address.app = 0x08004000.The bootloader reads the application’s initial stack pointer and reset vector from 0x08004000 and 0x08004004, respectively, and then jumps to the reset handler of

Hi all,currently iam using the stm32h757 controller.i want to use the FMC on both cores, in SRAM mode with this config: hsram1.Instance = FMC_NORSRAM_DEVICE; hsram1.Extended = FMC_NORSRAM_EXTENDED_DEVICE; /* hsram1.Init */ hsram1.Init.NSBank = FMC_NORSRAM_BANK1; hsram1.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE; hsram1.Init.MemoryType = FMC_MEMORY_TYPE_SRAM; hsram1.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_16; hsram1.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE; hsram1.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW; hsram1.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS; hsram1.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE; hsram1.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE; hsram1.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE; hsram1.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE; hsram1.Init.WriteBurst = FMC_WRITE_BURST_DISABLE; hsram1.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY; hsram1.Init.WriteFifo = FMC_WRITE_FIFO

Board: stm32h753zi nucleoFirmware & CubeMX: latest versionI have configured the adc to continous conversion and DMA output. The initialization fails in main.c in HAL_ADC_INIT. I stepped through the HAL lib and saw that LL_ADC_IsInternalRegulatorEnabled returns the HAL_ERROR.The docstring of this function says /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)I do not find any documents online which describe how the clock frequency of the adc should be set up. Could you please give me a hint.

im using STM32H753VIT6 MCU.I'm try to connect device using SWD in STLINK debugger but it will show "Error: Unable to get core ID" this Msgim checked MCU input voltage,im getting 3.3v .input power is oknow how can i debug this issue.SWD pins properly connected Vcc,Swclk,Swdio,Gnd into stlink debugger but why im getting this msg,kindly clarify

 STM32L071CBT6 GPIO PB15 Input Not Responding to 5V Signal from Buck ConverterHello everyone,I'm using the STM32L071CBT6 microcontroller and facing an issue with reading a digital input on GPIO pin PB15.What I'm Trying to Do:I’m using a buck converter with a 5V output to indicate the power status. The 5V output from the buck converter is connected to PB15, which is configured as a digital input on the STM32. Setup:Buck converter 5V output = GPIO PB15Measured with multimeter: PB15 shows 5V when buck converter is ONPB15 is configured in firmware as an input pin (floating or pull-down)Problem:Although PB15 is reading 5V on the pin when measured, the firmware logic that depends on PB15 being HIGH doesn't work. What I’ve Checked:The GPIO pin is correctly configured as inputMeasured 5V directly at PB15Tried enabling internal pull-down or external pull-down resistorNo response or logic change in the code when the 5V signal is appliedWhy does PB15 show 5V physically (confirmed v

Hi, I was trying to test the feature of "Level 2 flash lock" on my custom board. I'm having an unexpected behaviour.My total application consists of a bootloader responsable to load an application via CAN BUS through a custom communication protocol.Now, If I load my application program via CAN (via bootloader), the MCU can not set itself to level2 but remains set to level 1. If I transfer the same application with JTAG, the MCU can set itself to level 2 protection and any attempt to connect to it is correctly disabled. (in level 1 I can still connect by erasing the whole chip content). To give further informations, here is the code responsable to set level 2 protection implemented:FM_ClearFlags(); FM_Unlock(); flashSts = FM_CheckProtectionStatus(); if(flashSts == FM_FLASH_NOT_PROTECTED) // check current protection status { FM_SetOBConfig(); flashSts = FM_CheckProtectionStatus(); } FM_Lock(); void FM_ClearFlags(void) { FLASH->SR |= 0xE0; // clear the errors RDERR P

Hello,I read the UID from STM32L031K6P6 and each device returns the same result: 0x14473332, 0x38363437, 0x0.I read the value from the address given in RM0377 (0x1FF8 0050).Is the address given in RM0377 correct?I am attaching screen shots from CubeProgrammer.

I use the STM32CubeIDE platform and I need to insert into my project a routine that was able to update my firmware.What I need to understand is:I write the routine then I place it into the ITCMRAM and I run it; does it work ?Have I only to load into the flash (starting from the sector 0) the ELF file of the new firmware ?  Thank you, Carlo

Hi, I was looking at the following paragraph, because I`m trying to select a good crystal for my application, the situation is that I know that one importat point to be aware is that "gain margin ratio" needs to be bigger than 5, so to obtain this "gain marging ratio" the following formula need to be applied (gainmargin = gm/gmcrit), here "gm" is the "oscillator transconductance" (value shown in the image), my question is that if this value is a property of the MCU itself (of course the part of the embedded oscillator), or this "oscillator transconductace" has to be with the crystal used in the test,  because of the "characterization results" that paragraph states.As you can see in the paragraph the data was obtained in this way as the text states "All the information given in this paragraph is based on characterization results obtained with typical external components specified in Table 22 (inluding oscillator transconductance) " So I`m confused because I know I have to obta

Hi, I have set two ADCs on CubeIDE, for STM32G474CEU6 microcontroller, with DMA transfer. I am using ADC1 with timer 6 trigger out event and ADC3 with timer 7 trigger out event. The thing is, when I use timer 6 for both ADCs,  just for ADC1 or just for ADC3, they work just fine, but it seems that it is not capable of converting data using timer 7, as it never enters the dma conversion complete neither half conversion interrupt. I have also tried using different timers, but as long as they are not the same one  the ADC is not working. Both the reference manual and CubeIDE state that this timers are usable for these ADCs. Is this behaviour common? Should it be like that? As far as I understand, I should be able to use different sample frequency in different ADCs. In any case, why might this be happening? Thanks in advance.

I'm working with an STM32F412ZETx microcontroller and encountering an issue with the CAN2 peripheral. The transmit (Tx) functionality is working correctly, but the receive (Rx) interrupt via FIFO1 is not triggering at all.   CAN2 transmit works fine. I can see messages on the bus. same setup with CAN1 (Rx FIFO0) works fine. Is there anything specific I need to configure for CAN2 RX interrupts on STM32F412? Could the filter bank or SlaveStartFilterBank setting be causing this? Are there known limitations with CAN2 and FIFO1 on this device?

In the example ADF_AudioRecorder, the OutputClock.Divider is set to 4 (STM32Cube_FW_U5_V1.7.0\Projects\STM32U575I-EV\Examples\MDF\ADF_AudioRecorder\Src\main.c).But the datasheet RM0456 at page 1610 say: Fadf_proc_ck > 4 x FADF_CCKyWith Fadf_proc_ck = 4 x FADF_CCKy, this example doesn't respect the clock constraint.Who is correct ? the example or the RM ?

Hi All!I have a issue about SPI DMA communication on NUCLEO-H563 Board. Details are as follows.My Configuration of STM32CubeMx as shown in the figure1 and 2.figure1figure2I call the function of HAL_SPI_TransmitReceive_DMA(）, it comes to line 2212 of program and return HAL_ERROR then.I debug the program and find the value of hspi->hdmarx->Init.DestDataWidth is 0, so it return the error.Then I back to check the initialization of spi1 dma. I find that the Init.DestDataWidth of handle_GPDMA1_Channel2 is already 0 before execute statement __HAL_LINKDMA() .So I guess maybe somewhere my configuration of spi dma is wrong somewhere and I can't figure it out.Please help me for this question.Thanks!

OK, I have a STM32L462RE Discovery Kit (apparently a.k.a. B-L462E-CELL1).I am trying to get its sole Demonstration application to work (STM32CubeExpansion_CELLULAR_V7.1.0\Projects\B-L462E-CELL1\Demonstrations\Nx_TCP_Echo_Client), but I can’t even tell how it is supposed to work. I see “TCP_Echo_Client” in its name, so I assume if I have a simple TCP echo server running on my workstation that if I do the appropriate port forwarding through my router along with the appropriate Windows Firewall settings, then I should see the B-L462E-CELL1 connect to my local TCP Echo Server. Is that correct?Further, I assume that in this file:STM32CubeExpansion_CELLULAR_V7.1.0\Projects\B-L462E-CELL1\Demonstrations\Nx_TCP_Echo_Client\NetXDuo\App\tcp_echo_client.cI should change TCP_SERVER_PORT from 7 to whatever TCP port my local TCP Echo server is running on, AND I should change the TCP_SERVER_ADDRESS IP_ADDRESS(52,215,34,155) in that same file from 52,215,34,155 (which implies 52.215.34.155) t

Hi,it seems I have some general problem with the understanding of the SPI transmission with the STM32H5.I have an SPI, configured as master for transmission only. Initialisation and stuff is done by CubeMX-generated code, but the transmission shall be done more or less "manually". Means: I want to send 3x 1 byte by writing them one after an other into the related TXDR register.Now what I do NOT understand is, what flag do I have to wait for in order to see if a) I can write the next byte into the FIFO and b) see if all three bytes have been sent?From my understanding:a) can be achieved by waiting for the TXP-flag being set. As long as this is the case, I can write the next byte.b) can be achieved by waiting for the TXC-flag being set. As soon as this is the case, all data have been transmitted.However, there seems to be a dependency to the CR2-register. When I set it to 0,TXP appears once and then never again. When I set it to 3, TXC never appears.So I can't find a situation where

Hello!I have a custom board with NAND flash connected. One of the DMA channels is used during write operations to move data from RAM to FMC buffer (mem-to-mem mode). The channel has low priority so theoretically it shouldn't interfere with other channels. Second DMA channel (same DMA controller) with high priority is intended to receive ADC data (two ADC channels with x8 oversampling). DMA channel works in circular mode non-stop, ADC is triggered by timer (1kHz, single conversion, discontinuous mode disabled, ADC_REG_OVR_DATA_OVERWRITTEN mode, 92.5 cycles per conversion).The issue is an ADC overrun during NAND write operation (mostly not every operation but with certain periodicity) what results in missing value as if ADC channels were swapped. Besides these DMA channels, two more DMA channels are used on same DMA controller but the latter ones aren't active at the moment of ADC overrun. If you simply move NAND DMA channel to another DMA controller, the overrun disappears.This looks we

Question moved from this thread (a new question) Thank you very much for the solution. However, I’m still unclear about the core point. My main concern is that I need CAN files such that, when the code is flashed onto the STM32L4R9I-EVAL board, it should behave in the following way: upon receiving a CAN message, the board should either print something which is predefined or perform an action in response to that message. Could you please help me with this

Hi All,We are currently exploring microcontroller options to meet our system requirements. The system must support Ethernet communication at 1Gbps while simultaneously driving 24 GPIOs (12+12) with a single clock output at a speed of 38 MHz. All GPIOs should be updated on the rising edge of the clock signal and must be refreshed within half of the high duration of the clock signal, approximately 6ns.Additionally, the system requires high-speed external RAM to process data of approximately 1GB data. We have evaluated the GPIOs driving mechanism on one microcontroller, we encountered a bottleneck with the DMA clock source, as few clock cycles are required for proper DMA processing and updated GPIOs status by timer trigger event.We are seeking a microcontroller that meets these specifications and provides an efficient solution.Any suggestions will be appreciated.Thank you in advance.Jaydeep.