STM32 MCUs Security

Hello,I'm using AES-GCM using the method cmox_cipher_append() function call, as taken from the example below, taken from Projects\NUCLEO-L476RG\Applications\Cipher\AES_GCM_AEAD_EncryptDecrypt\Src\main.c        retval = cmox_cipher_append(cipher_ctx,                                    &Expected_Ciphertext[index], CHUNK_SIZE, /* Chunk of ciphertext to decrypt and verify */                                    Computed_Plaintext, &computed_size);     /* Data buffer to receive generated                                                                            chunk of plaintext */

Hi,I want to use the SBSFU application on the STM32U575ZIT6 microcontroller instead of the B-U585I-IOT20A board. Is this possible? If it can be done, what steps should I follow?

Hello @st_itI am taking the reference implementation of the HKDF Algorithm using PSA API in the TFM Application Project and using the following algorithm :PSA_ALG_HKDF(PSA_ALG_SHA_256);I m able to export the output key to the console and am getting an output for the test vectors taken from RFC5869 as shown below:But when using the same Hash, IKM, Salt, Info as given in the test vector set Im getting a different value as shown in the below format:(value displayed Derived Key Material is expected to be same as OKM in above Figure)The codes i have used the same format that was already present to be specific:TFM_Appli_NonSecure->Middlewares/trustedfirmware/test/crypto_tests_common.c : void psa_key_derivation_test(psa_algorithm_t deriv_alg,struct test_result_t *ret);Requesting your support to solve this issue and validate the HKDF Function ImplementationThanks and RegardsPhilip Jose

Hello, I am using STM32U585 TFM architecture for one of my project. Which basically is a combined project of 5 internal projects as usual TFM(mentioned below).1. TFM_Appli_NonSecure2. TFM_Appli_Secure3. TFM_Loader_NonSecure4. TFM_Loader_Secure5. TFM_SBSFU_Boot I have surpassed available RAM(SRAM1 of 192kb) for TFM_Appli_NonSecure project. And I am not getting any solution to this even after trying some ways like using SRAM3(mainly).I think now I need some export opinion for increasing this availablity by minimum of 50kbAny support any support will be appreciated. Thanks,Nitin  

Good afternoon,I am trying to encrypt some data using the AES peripheral and compare the results to the same operation in python and .NET. The cipher text output from the operation on the STM32 is different than that of the other two languages.The code I am testing is /** * @brief AES1 Initialization Function * @PAram None * @retval None */ static void MX_AES1_Init(void) { /* USER CODE BEGIN AES1_Init 0 */ uint8_t key[32] = {0}; uint8_t iv[12] = {0}; /* USER CODE END AES1_Init 0 */ /* USER CODE BEGIN AES1_Init 1 */ /* USER CODE END AES1_Init 1 */ hcryp1.Instance = AES1; hcryp1.Init.DataType = CRYP_DATATYPE_8B; hcryp1.Init.KeySize = CRYP_KEYSIZE_256B; hcryp1.Init.pKey = (uint32_t *)key; hcryp1.Init.pInitVect = (uint32_t *)iv; hcryp1.Init.Algorithm = CRYP_AES_GCM_GMAC; hcryp1.Init.Header = (uint32_t *)HeaderAES1; hcryp1.Init.HeaderSize = 1; hcryp1.Init.DataWidthUnit = CRYP_DATAWIDTHUNIT_BYTE; hcryp1.Init.KeyIVConfigSkip = CRYP_KEYIVCONFIG_ONCE; if (HAL_

Reference: STM32CubeExpansion_Crypto_V4..1.0, MCU: STM32G474REThe cmox_ecdsa_verify(...) function is failing with a fault code of 0x6c706, which is not contained within cmox_ecc_retvals.h header file. All arguments to the cmox_ecdsa_verify(...) function have been verified and the generated signature has been verified on the development platform. Perhaps the fault code definition in the source code (not available) will provide some insight into the problem? Are there any additional steps I can take to debug this issue?

Hi I have the project with the chip STSAFE_A110I don't need to development the application I just need to confirm the hardware is ok, for example, obtained the sn of the chip is successfully or other wayI don't want to add the stsw-safea1-mw to my project, There's no other easy way?

Hello,I have a project created with STM32CubeIDE that includes FreeRTOS.A Black Duck vulnerability scan was made on this project and a single vulnerability (CVE-2021-3420) was detected.This vulnerability describes a flaw in Newlib 3.3.0 (all versions before 4.0.0) which causes some newlib functions (mEMALIGn, pvALLOc, nano_memalign, nano_valloc, nano_pvalloc) to be unsafe with overflow conditions.All the files that are tied to this vulnerability by the scan are files sourced from arm-none-eabi that the IDE toolchain (GNU Tools for STM32(11.3 rel1)) uses to build my project.I am not sure how to fix this "vulnerability" in my project since I can't change how ARM implemented its build toolchain which STM32 is using.I am hoping I can somehow validate that my project does not use these compromised functions.From what I can tell, isn't this a problem for every user of arm-none-eabi-gcc?Am I doing something wrong? Can I somehow reject this vulnerability or fix it?Thanks.

In the X-CUBE-CRYPTOLIB v4.1.0, the documentation say that cmox_cipher_decrypt() accept the CMOX_AESFAST_CFB_DEC_ALGO as algo. But CMOX_AESFAST_CFB_DEC_ALGO is not defined, instead there is a CMOX_AESFAST_CFB_DEC_ALG in cmox_cfb.h.

How do you determine or configure the I2C address of the ST33PHF2XI2C? The data sheet does not explicitly state the devices I2C address, nor as far as I have read, described how to configure the address with strapping options either. Is there another document that I can be pointed to for this information?

HiI'm using the SBSFU example for the STM32U5 microcontroller. After an intrusion, the board enters a locked state. Is there a way to receive a notification when an intrusion occurs and another when it has ceased, indicating that the board can return to its original state?

Hi @Jocelyn RICARD I would like to generate Certificate Signing Request in my STM32H5 board, can i know which library i can use and share any document or example project 

rtos: zephyrMCU: STM32H723VET6Package: en.x-cube-classb-h7 v4.0.0I‘m working on make my program running on H7 to meet the requirements of Class B.The CPU and RAM test works well both on startup and run-time. I haven't prepared the CRC precalculated area and only want to see the Flash test failure, but the Flash test stuck at STL_SCH_RunFlashTM(). From CubeIDE I can get the stake message as belows. But I have no idea how to prevent it from fault. Thread #1 [main] 1 [core: 0] (Suspended : Signal : SIGTRAP:Trace/breakpoint trap)z_arm_usage_fault() at fault_s.S:80 0x802e808 <signal handler called>() at 0xfffffffd VerifyAllSections() at 0x8021b38 STL_TM_FLASH_RunTM() at 0x8021aa2 STL_SCH_RunFlashTM() at 0x8020d9e STL_RunFullTest() at classb_st.c:188 0x8027ce4 stl_classb_init() at classb_st.c:438 0x8027d80 z_sys_init_run_level() at init.c:247 0x8037394 z_cstart() at init.c:528 0x8037506 0x31538a and the final core registers value are: my source is totolly

Hello ST Community,I'm currently working on a project using an STM32 microcontroller and encountering a critical issue related to mbedTLS during SSL handshake processes. I’m seeking insights or solutions based on your experience with similar hardware configurations.Overview of the Setup:Microcontroller: STM32H735DKRTOS: FreeRTOSExternal Memory: HyperRAMProblem Description: The system functions perfectly with the FreeRTOS heap allocated in the internal memory—mbedTLS successfully completes the SSL handshake without any issues. However, when I configure the FreeRTOS heap to utilize external HyperRAM, the SSL handshake fails every time.Error Encountered: The specific error encountered during the SSL handshake is MBEDTLS_ERR_SSL_INTERNAL_ERROR with an error code of -0x6C00. This error occurs precisely during the mbedtls_ssl_setup, which configures the SSL context based on the given parameters.Steps Taken:HyperRAM Testing: I have confirmed that the HyperRAM is functional; other components s

Hello everyone, I hope you are well.I'm working on a project and one of the requirements is connection to AWS, so I chose to start with the STM32H573I-DK kit, where following the "STM32CubeExpansion_Cloud_AWS_H5_V1.0.0" step by step I managed to connect to AWS, however , the final micro used in the project will be the STM32H563ZI, so migrating the example to this micro, however, when I use "provisioning_auto.bat" at the end of the execution the following error appears in the "provisioning.log":'Starting SFIProcessing license...Get RSSe status...Processing Image HeaderGet RSSe status...Processing Area 1...Error: Execution of RSS CMD failed, returned value = 0xBF9F0F0Error: Failed to Process Area Number 1 of type HError: C:\ROT_Provisioning\SM\Binary\SecureManagerPackage.sfi SFI file Install Operation Failure! Please try again.'Can anyone help me with how to finalize the port?thanks in advance

Hello,I am working with STM32CubeU5 TFM v1.5 for STM32 u585. I develop a custom loader using CAN communication. First I used MCUBOOT_OVERWRITE_ONLY and MCUBOOT_PRIMARY_ONLY setup. The CAN communication worked fine (in non-secure loader).Then I switched to swap strategy (MCUBOOT_OVERWRITE_ONLY and MCUBOOT_PRIMARY_ONLY not defined). The CAN communication stopped working. After quite some investigation I found out that the reason is that the FDCAN IRQ is not enabled (although set to be enabled). Then I found out that the reason is probably due to the FDCAN1_IT0_IRQn is not set in ITNS1 for the non-secure domain. This can be handled in the secure loader.Unfortunately, in this mode the secure loader is not used. I am not sure why, did I misconfigure or misunderstand something? Any advise how to get interrupt enabled in the the non-secure loader in this mode?Thanx.Best regards,peter

Dear community,I have been experimenting with secure boot on the STM32H573I-DK using the latest git checkout of STM32CubeH5 (see https://github.com/STMicroelectronics/STM32CubeH5).The STiROT and OEMiROT examples run fine out-of-the-box. However, when I try to provision and run the STiROT_OEMuROT example, then the board seems to be in a boot loop. When I insert a "while (1) {};" line after https://github.com/STMicroelectronics/STM32CubeH5/blob/main/Projects/STM32H573I-DK/Applications/ROT/OEMiROT_Appli_TrustZone/Secure/Src/main.c#L135 , the boot loop stops. So it seems to be a hard fault when the jump to non secure code is made.Note that I am using the code as it is checked in with Git: no changes were made to the example code.Can anyone help me in debugging this code? I have already followed the tutorial on https://wiki.st.com/stm32mcu/wiki/Security:How_to_start_with_STiRoT_OEMuRoT_on_STM32H573 multiple times, line by line.Best,Jens

I get a 404 Not found for this ST URLhttps://wiki.st.com/stm32mcu/wiki/Security:Introduction_to_Manufacturing_for_STM32H5I'm specifically looking for the manufacturing flow with chip-specific licenses

I'm interested in understanding the modifications required to adapt the 'STM32Trust security framework' code, accessible on the STM website for STM32L5, for my project of developing a secure bootloader code specifically designed for the STM32G070RB. Has anyone tried this? Please suggest me how to do? the link I referred is "https://www.st.com/content/st_com/en/support/learning/stm32-education/stm32-moocs/STM32_security_ecosystem.html"

For storing my crypto key I'm using the following function to store the key in the WB55 core 2 secure key storage:uint8_t key_index = 1; SHCI_CmdStatus_t result; SHCI_C2_FUS_StoreUsrKey_Cmd_Param_t CKS_param; CKS_param.KeyType = KEYTYPE_SIMPLE; CKS_param.KeySize = KEYSIZE_32; memcpy(CKS_param.KeyData, key, KEYSIZE_32); result = SHCI_C2_FUS_StoreUsrKey(&CKS_param, &key_index); DPRINTF("Key stored at index: %d", key_index);And than loading it into the aes crypto peripheral.Al works fine until the index reaches the end positions(100 keys).After that writing a new key will always fail.I can't find a function to wipe the user key(s).I there a way to achieve this? How can i wipe or overwrite a user key?I think I misunderstand the use of CKS...

From AN5185 I understand that up to 100 keys can be send to FUS for storage, but any index will only be written once. So once I have reached 100 writes, e.g. because I have constant pairing keys between devices but I allow to disengage and reengage such pairings, I can no longer save any keys in FUS and would have to rely on handling by CPU1. Is this correct?

Hello,I'm struggling to find any information regarding possibility to remove the keys stored through FUS CKS.My understanding is, if the keys are constantly being stored to some reserved space in flash memory, this reserved space will eventually be full and another key write will be impossible.I found two related threads with no answer to this problem: https://community.st.com/t5/stm32-mcus-security/stm32wb-fus-cks-no-option-to-delete-or-overwrite-userkeys/td-p/586508https://community.st.com/t5/stm32-mcus-security/how-can-i-wipe-user-key-fus-ws-cks-when-all-index-positions-are/td-p/62762Is it possible at this point to add key removal to the API? Is such feature planned?Regards,Larry

I have a strange issue here. I'm trying to do a short, blocking, UART transmission.I have a 23 byte uint8_t array ( MSG ) that I construct before calling the HAL_UART_Transmit() function to send the data. (SLAVE_MSG_SIZE = 23, UART is a pointer to the UART4 object)HAL_UART_Transmit(UART, &MSG, SLAVE_MSG_SIZE, 1);The problem is that it never sends just 23 bytes, its sends more, sometimes less, but almost always more. Most I've seen is around 46 bytes, which is close to 2x, which may be a clue to what is going on.(The receiver side can handle extra bytes at the end because it just doesn't look at them, but when the TX packet is too short, the 2 CRC bytes are absent and the CRC check fails.)The strange thing is that if I manually set the "data size" parameter in the HAL call to 15 bytes or less, I get the expected, truncated data of the correct length. However, if the size argument is >15 bytes, the amount of transmitted data is always more than the expected value.My code is the fo

I'm porting my project(sbsfu Nucleo-h753zi to Nucleo-h745zi-q)and i checked protection my board, but i can't full chip erase../STM32_Programmer_CLI.exe -c port=swd mode=UR -ob PROT_AREA_START1=0xFF PROT_AREA_END1=0 RDP=0xAA-------------------------------------------------------------------STM32CubeProgrammer v2.16.0-------------------------------------------------------------------ST-LINK SN : 003900363137511039383538ST-LINK FW : V3J14M5Board : NUCLEO-H745ZI-QVoltage : 3.27VSWD freq : 8000 KHzConnect mode: Under ResetReset mode : Hardware resetDevice ID : 0x450Revision ID : Rev VDevice name : STM32H7xxFlash size : 2 MBytesStart Address : 8000000Device type : MCUDevice CPU : Cortex-M7/M4BL Version : 0x90UPLOADING OPTION BYTES DATA ...Bank : 0x00Address : 0x5200201cSize : 308 Bytes栢栢栢栢栢栢栢栢栢栢栢栢栢栢栢栢栢栢栢栢栢栢栢栢栢 100%PROGRAMMING OPTION BYTES AREA ...Warning: Option Byte: rdp, value: 0xAA, was not modified.Bank : 0x00Address : 0x5200201cSize : 308 Bytes栢栢栢栢栢栢栢栢栢栢栢栢栢栢栢栢栢栢栢栢栢栢栢栢栢 100%UPLOADING OPT

Hi ChannelI have tested the TF-M Package Released by ST, on the STM32U585 and its working fine. Now i want to revert back my STM32U585 (B-U585I-IOT02A Kit) as for the testing of TF-M SBSFU there is some configuration of option bytes as given in UM2851 manual.Now i want to test some normal applications on the same board. I have made the following changeschanged RDP to to 0 and changed TZEN bit =0 at the same time to disable the trust zone controller.i have disabled wrp 1 and wrp2 bits.But now i am not able to do a full chip erase and am not able to any other program (for example led test or UART test example).Kindly help me out in the clear procedure on how to revert back the option byte configuration to the default one.Thanks for the support