Incorrect CPSIZE for STM32MP1 FMC I am using the FMC peripheral of the STM32MP157 to access the FPGA, the FMC is configured as a Synchronous read synchronous write PSRAM. For the simplicity of the FPGA logic design I would like to have the burst reads and burst writes with CRAM page size (CPSIZE) fixed at 1024 bits.This is the device tree configuration: &fmc {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&fmc_pins_mx>;
pinctrl-1 = <&fmc_sleep_pins_mx>;
status = "okay";
psram@0,0 {
compatible = "mtd-ram";
reg = <0 0x00000000 0x100000>;
bank-width = <2>;
st,fmc2-ebi-cs-transaction-type = <8>;
st,fmc2-ebi-cs-cclk-enable = <1>;
st,fmc2-ebi-cs-mux-enable;
st,fmc2-ebi-cs-buswidth = <16>;
st,fmc2-ebi-cs-clk-period-ns = <60>;
st,fmc2-ebi-cs-cpsize = <128>;
st,fmc2-ebi-cs-data-latency-ns = <0>;
st,fmc2-ebi-cs-write-bus-turnaround-ns = <0>;
st,fmc2-ebi-cs-max-low-pulse-ns = <0>;
};
psram@1,0 {
compatible
