STM32 MPUs Products and hardware related

Due to the high cost of RAM. I wonder if ST have plans or other information about which 4GB RAM vendors fits MP25x products?I know that ST have information about other RAM vendors on their wiki. Only one 4GB vendor is mention there.I bought the 4GB RAM MT53E1G32D2FW-046 WT:C (single rank) from here when it cost 20 USD.https://www.aliexpress.com/item/1005009146059053.html but its seems to only having the DDR density to 8bits (2 GB). Perhaps it was only a 2GB or MT53E1G32D2FW-046 WT:B (dual rank)I'm still looking for other RAM vendors that can offer 4GB solutions for the MP25x. Question:Can ST write a criteria what a RAM memory need to have to fit MP25x? Do the RAM need to follow a specific RAM standard? What do I need to know to know if the RAM memory fits the MP25x? 

Hi everyone,I am encountering an issue while trying to flash OpenSTDroid onto my STM32MP257F-DK board.I downloaded the Starter Package from the official website and used STM32CubeProgrammer for the installation. However, the flashing process consistently fails during the final stages.Could anyone provide the correct flashing procedure or suggest what might be causing this error? Below are the details of my setup:Starter Package Source: STM32MP2DroidSta | Product - STMicroelectronicsSTM32CubeProgrammer Error Screenshot:   Thank you in advance for your help!

Hello Every One,Hardware / Software EnvironmentBoard: STM32MP257F-EV1Device: STM32MP257FAIxIDE: STM32CubeIDE v2.0.0 (Windows)Firmware package: STM32Cube FW_MP2 v1.2.0OpenSTLinux version: openstlinux-6.6-yocto-scarthgap-mpu-v25.06.11What I DidFlashed OpenSTLinux image to eMMC using USB DFU with:FlashLayout_emmc_stm32mp257f-ev1-ca35tdcid-ostl-optee.tsvFlashing completed successfully.Linux boots correctly and I can log in via UART:root@stm32mp2:~#Created a simple GPIO project for Cortex-M33 using STM32CubeMX and STM32CubeIDE:Selected MCU: STM32MP257FAIx (not board)Selected “M33 Master”Toolchain: STM32CubeIDEProject builds successfully without errorsLinker Memory ConfigurationThe generated linker script places CM33 firmware in DDR memory:NS_VECTOR_TBL : ORIGIN = 0x80100000FLASH : ORIGIN = 0x80100600RAM : ORIGIN = 0x80A00000VIRTIO_SHMEM : ORIGIN = 0x812F8000IPC_SHMEM_1 : ORIGIN = 0x81200000So the CM33 firmware is located in DDR (0x80xxxxxx region).ProblemWhen attempting to debug or download

In my custom FSBL on an STM32MP135AAE3, everything runs great except anytime I try to modify one of the GIC flags it pretty much ignores me completely (when I read it back, my changed bits aren't changed).  I'm guessing this is some kind of trust zone or secure state or similar situation.BTW, when I run my FSBL by setting the chip to serial boot and uploading it that way, it runs great, so I know the code is solid.What do I need to change so my FSBL has full privileges?  Is there a document that talks about this?

Does the stm32mp157 have an ESV or is there one in progress? 

Hello everybody.On STM32MP2, is it possible to operate only the M33 like a microcontroller, without booting the A35? Also, if only the M33 is operated, can major peripherals such as I2C and Ethernet be controlled from the M33? (I assume that PCIe would be difficult...)

I am building a custom Yocto image for STM32MP1 (STM32MP157) using ST OpenSTLinux (dunfell-based) and I am facing a persistent U-Boot build failure.Environment:SoC: STM32MP157 (custom board)Yocto: ST OpenSTLinux (dunfell)U-Boot: v2020.10-stm32mp-r2.2Recipe: u-boot-stm32mpMachine: stm32mp1 Issue:During bitbake u-boot-stm32mp, the build fails in do_compile with the following error:.../tmp-glibc/work-shared/stm32mp1/uboot-source is not clean,please run 'make mrproper'This error is triggered by U-Boot’s internal check that aborts when generated files are found in the shared source tree. Observations:The error occurs even after running:bitbake -c clean u-boot-stm32mpThe failure persists until I manually remove:tmp-glibc/work-shared/stm32mp1/uboot-source and then run:bitbake -c cleansstate u-boot-stm32mp At some point earlier, I ran make menuconfig manually in the U-Boot source to inspect SPI configuration, which may have introduced .config or include/config/* into the sh

I've got an STM32MP135AAE3 for which I'm writing my own FSBL.  It's basically working!There are two scenarios:1) Chip set to serial boot; the BootROM wakes up and I use STM32_Programmer_CLI.exe to send it my FSBL which it stores in SYSRAM, BootROM then passes execution to my FSBL2) Chip set to boot from eMMC; BootROM wakes up, sees my FSBL in eMMC, copies it from eMMC to SYSRAM, passes execution to itIt would be helpful for my FSBL to know which scenario it is, and according to STM32 MPU ROM code overview I should be able to inspect the first 512 bytes SRAM2 for a bunch of boot information as defined in this H file.  It also says SRAM2 is for "ROM code secure data" and SRAM1 is for "ROM code non-secure data" and I'm running in non-secure mode so maybe it's actually SRAM1 for me?In any case, I've got my LD file set up so nobody touches the first 512 bytes of either SRAM1 or SRAM2:MEMORY { SYSRAM (rwx) : ORIGIN = 0x2FFE0000, LENGTH = 128K SRAM1 (rwx) : ORIGIN = 0x3

Hello,unlike the STM32MP157F-DK2 the STM32MP257F-DK is not equipped with an Touch/LCD.Is it possible to use an identical/similar LCD with the STM32MP257F-DK (that means: are the appropriate connections on the board)?Marc

Linux kernel, Yocto project, etc. each has their LTS strategy, does ST has similar plan for its OpenSTLinux?

Hi,I am trying to understand and test secure boot on STM32MP1. I was able to compile and boot unsigned tf-a. boot failed as expected as it is not verified.generated keys.Now how to burn these below hash file? can we burn into flash and test without using OTP for development and POC?publicKeyhash.binThank you.

  Hello Team,I am currently working on QuadSPI with MDMA, but I am unable to locate the driver code for this functionality.Could you please provide the required driver code?For reference, I am working on the STM32MP133F series.Regards,Sreedhar Kaduru  

Hello,Is there a list of supported/recommended displays that are compatible with the DSI connector CN4 on STM32MP157D-DK1 please?Kind regards,Al  

I've got a custom board with an STM32MP135AAE3 talking to an eMMC (THGBMTG5D1LBAIL if it makes a difference). I've discovered that if I write from SYSTEM to the eMMC using DMA (HAL_MMC_WriteBlocks_DMA) it works fine, but if I use anything in RAM (SRAM1, SRAM2, or SRAM3) as the source, the DMA fails immediately.If it helps, the SDMMC2 registers inside SDMMC2_IRQHandler() are: STA=0x8001010; DCOUNT=0x200; DCTRL=0x90; IDMACTRL=0x1; MASK=0x11AIs this a known limitation of the IDMA? If not, is it something I'm somehow initializing incorrectly?

Hello ST Team,I am evaluating the STM32MP215F-DK with the recommended M.2 Wi-Fi/BT module (Embedded Artists EAR00409 / Murata 2EL). I have encountered two critical issues that prevent the Wi-Fi features from working out-of-the-box with the standard Starter Package.I believe these are bugs in the current hardware/software release.1. Critical Software Configuration Issue: SDMMC2 Access Blocked by RIFThe STM32MP215F-DK Data Brief explicitly states that the board features an "M.2 E-Key connector to support Wi-Fi® and Bluetooth® SDIO modules". However, with the default Starter Package (OpenSTLinux 6.6), the Linux kernel fails to probe the Wi-Fi module on SDMMC2.Symptoms:• Linux kernel log shows no response from mmc1 (SDMMC2).• Attempting to access the SDMMC2 registers manually via devmem 0x48230000 results in a Bus Error.• OP-TEE console reports a firewall exception: SERC exception ID: 77 (SDMMC2 Illegal Access).Root Cause Analysis: It appears that the Trusted Firmware-A (TF-A) device tree

Hi,We are trying to make use of the ethernet interface in this fashion:- The board is a custom one with a soldered module from Karo, the qsmp-2550, that includes an stm32mp255fa.- The eth2 is connected to a PHY (TI DP83869HM) in RGMII.- The PHY is then configured to output Base100-FX to an SFP cage.- There is no CLK125, we use ck_ker_eth2 configured at 125Mhz (confirmed in /sys/kernel/debug/clk/stm32_clk_summary), we use the `st,ext-phyclk` DT property.The PHY is reachable via mdio using the CLI from mdio-tools and seem to be working as intended.We checked that the PHY sends the correct clock, the RX one, with a scope: it does.Then when enabling the link using `ip link set up eth0` we are greeted with:```root@qsmp-2550:~# ip link set up eth0[ 16.583371] stm32-dwmac 482d0000.eth2 eth0: Register MEM_TYPE_PAGE_POOL RxQ-0[ 16.586971] stm32-dwmac 482d0000.eth2 eth0: Register MEM_TYPE_PAGE_POOL RxQ-1[ 17.123948] stm32-dwmac 482d0000.eth2 eth0: PHY [stmmac-1:00] driver [TI DP83869] (irq=

Hello ST community,I’m an embedded software beginner working with the STM32MP257-DK board and OpenSTLinux (Yocto). I need help getting USART6 working on the external GPIO connector (PF13 = TX, PF14 = RX — CN5 pins). I have rebuilt device trees and copied DTBs to the board, but the USART6 device never appears in the running system (/dev/ttySTM6), and at one point my Ethernet/SSH stopped working after applying a DTB change.I will be blunt: I have spent many hours following suggestions, debugging, and fixing syntax errors in DTS files. I may be missing one critical detail about how ST maps peripherals on the DK board or about kernel bindings. I have documented exactly what I tried and the exact outputs — please read fully before replying. I am a beginner; please do not assume I know advanced DT or U-Boot internals.Environment / versionsBoard: STMicroelectronics STM32MP257F-DK (discovery/“DK” board)Host SDK: SDK-x86_64-stm32mp2-openstlinux-6.6-yocto-scarthgap-mpu-v25.06.11Kernel source / s

I have built a custom board by using STM32MP257F and I want to boot on USART6. I have not succeed to boot on USART6 when I compile my own fsbla by change the device tree of TF-A.I got a suggestion from ST Dev team to run this ROM tracedump wiki-stm32mp-addons/MP2RomTracesDump at 6.1.0 · STMicroelectronics/wiki-stm32mp-addons · GitHub and it gave me a positive output on USART6. The soldering was OK. The BootROM was OK and the UART6 was alive. This is the output from my USART6.=================================================== == STM32MP25 cut2.x bootrom display traces V1.01 == == Date of compilation : Jun 26 2024 - 11:25:23 == =================================================== Executed on Cortex A35 - Aarch64 Successfully booted on interface SD instance 1 Reset reason : POR reset Chip state : CLOSED_UNLOCKED ================================================================== Bootrom traces ================================================================== [INFO] -

Hello, I am working with an STM32MP135f-dk device running Linux and trying to evaluate the possibility of using the USART peripheral in synchronous mode (TX/RX + CK). From a hardware point of view, the STM32 USART clearly supports synchronous operation. However, when using the standard STM32 USART Linux kernel driver, the peripheral is only exposed as a /dev/ttySTM* device and operates strictly in asynchronous (UART) mode. As far as I can see, the current driver does not enable or drive the CK clock signal, which makes true synchronous USART communication impossible under Linux, even though the underlying hardware is a USART. My questions are:1. Is this limitation expected by design in the current STM32 Linux USART driver? 2. Has anyone successfully implemented synchronous USART on STM32 under Linux, for example by: Extendimg the existing driver, writing a custom kernel driver, or using an alternative ?

Hi,I'm using brand-new, unmodified st32mp257f-dk dev board.When using starter package (https://www.st.com/en/embedded-software/stm32mp2starter.html#get-software) flashed onto sdcard according to https://wiki.st.com/stm32mpu/wiki/How_to_populate_the_SD_card_with_dd_command, system boots-up fine, see 'downloaded_no_panic.log'. Version is openstlinux-6.6-yocto-scarthgap-mpu-v25.06.11.When using image built on my own - distribution package  (openstlinux-6.6-yocto-scarthgap-mpu-v25.06.11)  according to https://wiki.st.com/stm32mpu/wiki/STM32MPU_Distribution_Package, using docker, I get following:[ 8.296788] usb 1-1: new high-speed USB device number 2 using ehci-platform [ OK ] Found device /dev/hwrng. [ OK ] Found device /dev/tee0. [ 9.041963] hub 1-1:1.0: USB hub found E/TC:0 0 Panic at /usr/src/debug/optee-os-stm32mp/4.0.0-stm32mp-r2/core/drivers/clk/clk-stm32mp25.c:2000 <clk_stm32_pll_init> [ 9.142742] hub 1-1:1.0: 2 ports detected E/TC:0 0 TEE load ad

Dear All,I have a total of 8 boards with eMMC from Alliance Memory. All of them boot from SDCard and work well. On 4 of them eMMC is detected correctly and boots fine with 50Mhz/8bit/ddr speed.4 boards are failing in exactly the same manner, that is:  EXTCSD/CID registers have some wrong values and eMMC is discovered as 128MB (instead of ~4GB), with with wrong manuf. ID and manufacturer code. Writing gives io-error (timeout) - reading returns "ER18" ascii code every 512bytes.I have lowered down params of sdmmc interface down to: 400kHz / 1 bit / no-ddr, with different slew-rates on IO ports without a success. I've observed these changes on an oscilloscope and also with simple logic analyzer on lower speeds/1bit bus. Failure is persistent between restarts and also between boards. I have also manipulated series resistors and pull-up resistors.Normally I'd expect some layout issues, but this failure mode is really stable and I am looking for other ideas. I can't imagine tha

Please check STM32MP157F-DK2 no function issue after STM32MP157F-DK2.#1. After receiving the STM32MP157F-DK2 board, I connected a 5V/3A Type-C Power Adapter to CN6 and verified Linux boot and operation. LCD operation.#2. Updated the Linux image on the SD card using STM32Cube Programmer on a Windows PC.Following the procedure in the link below, successfully updated the Linux flash image to the SD card using FlashLayout_sdcard_stm32mp157f-dk2-optee.tsv via STM32Cube Programmer on the Windows PC.https://wiki.st.com/stm32mpu/wiki/Getting_started/STM32MP1_boards/STM32MP157x-DK2/Let%27s_start/Populate_the_target_and_boot_the_image#3. Turn SW1 BOOT0 and BOOT2 back ON, connect the USB Cable to the ST-LINK (CN11) on the PC, and connect the 5V/3A Type-C Power Adapter to CN6 to boot the stm32mp157f-dk2 board.#4. UART logs output normally, but the message "ERROR USB TYPE-C connection in unattached mode" appears and Linux does not boot. - The same Type-C Power Adapter used in #1 above was

Hello I am planning to use STM32mp257Fak3 with DDR3L (16bit and 32 bit saperately),can you suggest some DDR part no and it's sonnection.

Hello,I am working with an STM32MP151 and I would like to start the Cortex-M4 core as early as possible during the boot sequence.The main requirement is to run a real-time task on the M4 that reads an analog input (ANA0 – ADC channel) with minimal startup latency.In my current setup, the ADC channel is first owned by the Cortex-A7 Linux kernel and is explicitly released and reassigned to the Cortex-M4 via the Linux device tree (by disabling the ADC node for A7 and assigning it to the M4).Additionally, if I stop the system in boot mode and manually start the Cortex-M4, I am able to successfully debug the M4 firmware and correctly read the ADC value.My goal is to have the M4 firmware start automatically in the same early boot conditions, without requiring a manual boot/debug sequence.I would like to understand:At which earliest boot stage the Cortex-M4 can be releasedWhether the Cortex-M4 can be started independently from the Linux boot on the Cortex-A7Thank you in advance for your suppo

Hello,Currently I'm working on a project that requires a synchronized clock signal between multiple devices connected through Ethernet.The logic solution for this is PTP, and using linuxptp I was able to archive synchronous PPS on PG8 pin between devices with a jitter smaller than 1us for 1Hz. Now the problem is that the requirement for PPS frequency is not 1Hz but a OR between a 100Hz and 1.25Hz (see attached image). From documentation, flexible PPS output may be the solution and started testing it by generating the 100Hz signal. Here is were I found the issue, after program PPSCMD[3:0] with start I notice that the 100Hz signal starts to drift slowly (around 20us/s).Now strange part is if I use fixed PPS (bit PPSEN0 of MACPPSCR cleared) with any frequency (1Hz to 16kHz with digital rollover) there is  no drift. From my understanding the reference clock for pps is the same as system time thus adjusted by ptp protocol for maintaining synchronization.Is my assumption corre