STM32 MCUs Products

Hi everybody,I read 15 analog channels with DMA on my STM32f446. It works very well (It's tiggrered by TIM3 every 200ms).So I'd like to add Vbat. First, I've added it as the 16th channel of DMA, it works, but I saw the battery voltage decreases (around 0.05V in two hours), so I think I read it too often.So I'd like to read it periodically (every minute for example).I'm trying to read my 15 first channels with DMA and then a classic read for Vbat, but the value is always wrong (around 560 instead of 1000).Is it possible to do that (two different means to read ADC) ?Thank you,

Hi ST team,I am seeing what appears to be a silicon-level issue on STM32H563RGV6, revision X, related to the SWAP_BANK option byte.When SWAP_BANK is enabled, a USB OUT endpoint stops being re-armed during a flash mass erase of the inactive bank. The USB ISR still executes, but the BULK OUT path wedges because the OUT endpoint is no longer re-armed. Once the mass erase completes, the endpoint behavior returns to normal.Key observations:MCU: STM32H563RGV6Revision: XThe issue is specifically tied to SWAP_BANK being setThe problem occurs during mass erase of the inactive bankThe symptom is specifically USB OUT not being re-armedThis does not look like a total USB interrupt loss; ISR activity can still occurOther endpoint activity is not affected in the same wayThe entire application, including vector table and read-only data used by the relevant path, is relocated to SRAMBank selection / inactive-bank arithmetic has been verified and is correctThis does not appear to be a normal software i

Hi,  I have an stm32g473 which use the clock of another system as external clock on PF0 / OSC_IN. This clock is them multiplied by 74 through the PLL. I need to synchronize my code with the external clock (i.e. wait for it to rise).  What is the simplest way to do this? Can I use PF0 both as OSC_IN and as an GPIO in input mode to generate an event on the rising edge? or should I root the clock to both OSC_IN and another GPIO?  Are there other possibilities did not find in the reference manual (e.g. using the HSE as a trigger to one of the timer or an event I could WFE on ?)Thanks.

I was wondering if there is any possibility to change the NCS from NCS1_port2 to NCS2_port2 using the OTP registers on the STM32N6.I checked the registers but couldn’t find any option to adjust this. Maybe its not possible. Just to confirm my understanding:The default setting for ROM boot is XSPI1 using XSPIM_Port_2, and NCS1 is "required" by the ROM boot code to correctly load the FSBL via LoadAndRun. https://community.st.com/t5/stm32-mcus-products/stm32n6-it-s-possible-to-change-xspi2-to-xspi1-for-boot-using/m-p/847884/highlight/true#M287378 Kind regards,Zimmeri

Dear ST,The STM32H5 overview page seems to display the wrong number(1) of CANFD controllers for STM32H5E4 in the line comparison table. The datasheet says it's 3,  like for all the others  in the STM32H5E/F lines.Also, I couldn't find anything in the errata sheet about non usable CAN instances.

 Hello Forum,I want to use a Nucleo 64 STM32F401 Board to test I2C connection with an unknown master (reverse engineering).The Bus consits of 1 Master (unknown Controller) an 1 Slave (My STM32F40). The Master sends out a Read Request at Addr. 5 and the Slave should respond with 3 Bytes. I've connected the I2C Bus to PB6/PB7 of the Nucleo Board. On Softwareside I Initialized with bare metal Code, see attachment.I my setup a I2C Master sends out a Adress byte with read request to address 5, but my Controller doesn't do a thing at all. I would expect at least an ACK Bit, but nothing can be monitored.From the Signal capture the bus looks fine for me, but in which mode do I need to configure the stm32 slave? Is this standard mode or fast mode. Is the clock speed of any concern in this case (slave)? How to config the CCR and TRISE register in this case.The Port seems to be configured correct, the IDR of GPIOB detects a "1" on PB6/PB7.In my example I've also enabled interrupts, but

Hello,We programmed our STM32L011 microcontroller with firmware that enters STOP mode and waits for an interrupt.However, we accidentally disabled the interrupt on the PA4 line. As a result, the device now immediately enters STOP mode, and we are unable to reprogram it.Could you please advise how we can recover the device in this situation?Thank you in advance.

 Hello!We are using an STM32L0 microcontroller as a power switch.The device works correctly when the firmware is started from STM32CubeIDE using the Run command.However, if we switch the power supply off and then back on, the STM32L0 does not boot.We suspect there may be an issue related to the reset circuit.Please see the attached schematic. The relevant device is U6.Could you please advise?Thank you in advance.

Hi,I am testing PD11 on an STM32H563ZI with a NUCLEO-H563ZI board.The pin is configured as plain GPIO input using STM32 HAL:GPIO_InitStruct.Pin = GPIO_PIN_11; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_PULLUP; // or GPIO_PULLDOWN / GPIO_NOPULL HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);I rebuild and reflash the firmware for each case, then read the pin with HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_11).What I observe is:GPIO_MODE_INPUT + GPIO_PULLUP -> LOWGPIO_MODE_INPUT + GPIO_PULLDOWN -> HIGHGPIO_MODE_INPUT + GPIO_NOPULL -> LOWI also checked the pin with a multimeter, and the measured pin level matches what the MCU reads.I have rebuilt and reflashed multiple times and I keep getting the same pattern.My expectation was that a floating input with internal pull-up should read HIGH, and with internal pull-down should read LOW.Is there anything special about PD11 on NUCLEO-H563ZI / STM

Background: I am designing a high-speed imaging system for an industrial press. I am using an STM32 to synchronize a camera (TIM3) and two flashes (TIM4) based on an external hardware trigger.The Setup:Both timers are in One-Pulse Mode (OPM) and Combined Reset + Trigger Mode (SMS = 1000).Both are triggered by the exact same physical edge using HAL_TIMEx_RemapConfig(&htim4, TIM_TIM4_ETR_TIM3_ETR)The digital filter is set to 16 µs for both (ClockDivision = DIV4, TriggerFilter = 0xf).The Goal: When a valid trigger arrives, both timers start automatically. TIM3 fires its pulse almost immediately. TIM4 counts down a configurable delay (via CCR) before firing the flashes.To prevent mechanical double-triggers from the sensor, I need a firmware "blind window." Once the initial valid trigger is received, I want to completely ignore the ETRF pin for a few milliseconds.The Catch: I want to disable the ETR input from inside TIM3's HAL_TIM_PWM_PulseFinishedCallback (which fires right after the

I'm looking at Rev 9 of the STM32L412xxx Datasheet, as linked on Digikey, and I'm having a hard time understanding the current consumption figures specified for the Low-power Run & Low-power Sleep modes on the MCU.  Per the table on pg.24 (shown below), the current draw is 83uA/MHz in LPRun mode, which is higher even than the normal Run mode up to 26MHz (range2), which doesn't make sense to me.  Further, the current draw in LPSleep mode is also 83uA/MHz, which suggests there's no power savings putting the MCU to sleep in Low-power mode?  Can somebody tell me what I'm missing here, or is this a typo and one or both of those figures are wrong?

I am using the STM32H753VGT6 microcontroller and need to generate two PWM signals with the same frequency and duty cycle, with a 90-degree phase shift between them, using a single timer. Is this possible? If yes, how can it be achieved?

Dear Team ST,We are using the STM32 MCU (Part No. STM32F407VET6) on our custom board, and we are currently facing an issue related to the reset function.During board power-on or after program loading, the MCU appears to enter a hold or non-responsive state. This issue occurs every time the board is powered OFF and then powered ON. However, when the hardware reset button is pressed, the MCU starts functioning as expected.We kindly request your support in identifying the root cause of this issue. Please advise if any modifications are required on the firmware or hardware side to resolve this behaviour.We look forward to your guidance.Regards,Kaushik@Shubham Prakashpant BOHARAPI

I would like to enable spread spectrum on the STM32H573RIT6.We are currently running on 250Mhz and at that frequency we have big peak which is 15dB above the limit, that's why I would be able to enable the spread spectrum. I looked into the STM32H7 example, so I am already aware and able to modify the PLL realtime. Now my question is how do I connect the DMA of the STM32H5 properly to a timer and a buffer to load the PLL. And also a question I have, what are good values for the PLL.  

Hello,I must implement a SSI (Synchronous Serial Interface) to output a measured value. As SSI in principle is just a bitstream which is clocked out with the serial clock, I wanted to use a SPI in slave mode, as the clock comes from the SSI master.This works in principle, but from time to time I get a bit shift and the received data is delayed by one bit, which results in a division by two.Checking the SSI data clock, I didn't find an expected unstable clock with additional edges but from time to time the SSI master makes a pause after the first falling edge before it starts clocking. Could it be that this pause disturbes the SPI interface? I would have expected, that the SPI in slave mode only checks the clock edges and that the time between the clock edges isn't that critical?

Hi,During the design with the STM32H743IIK6 MCU few questions arise:(1)  While designing a PCB with the STM32H743IIK6 (UFBGA176+25 package) with VDD=3.3V or 2.8V, I am unable to locate the VCCLDO pin, which is expected to be connected to external capacitor. Am i missing something in the pinout, or does the internal LDO in this specific package rely solely on the capacitors on the VCAP pins?(2) There are two sets of QUADSPI I/O sets: BK1 and BK2 (i intend to use the BK2). However, I do not see any separate clock pins for each. Do both channels share the same QUADSPI_CLK signal for both banks?(3) Regarding the USB interface: I see a VDD33USB pin, but there is no VDD5USB pin. Does this require an external 3.3V DC input, or is it an internal signal output that only requires a decoupling capacitor?Additionally, I am unable to locate the USB_DP and USB_DM pins on the UFBGA176 package. Is there specific hardware documentation / example schema that clarifies the physical lo

The problem is that the transceiver will set the RX pin high at boot , this will put the G431 in boot mode and never start . The question is how to set and reset the nSWBOOT0 bit in the program . I mean , if I am right ::2) at setup (yes , Arduino) , the nSWBOOT0 bit is set in order to disable BOOT0 pin , thus allow normal (CAN bus) operation after boot  on PB8 .1) but this will reset the STM32 , so before doing 2) , one need to read the level of nSWBOOT0 , and only set it if it is 0 . (one time action)3) but this will brick the DFU uploading . To reset this , for exemple by a customer In order to update the firmware , one have to reset the nSWBOOT0 by the program . This could be done by a button , or by a code received trough USB .Hope this is clear enough (and correct of course) . But doing this is not that simple for me , so I wonder if there is a working code available for this (sure , some people have done the trick successfully ) ?Thank you !Edit : c

NUCLEO F767ZI, CubeIDE 2.1.1, CubeMX 6.17.0I'm trying to set up UART with printf()#include <stdio.h> UART_HandleTypeDef huart3; static void MX_USART3_UART_Init(void); int __io_putchar(int ch) { HAL_UART_Transmit(&huart3, (uint8_t *)ch, 1, 10); return ch; } .... // in main // in while prinf("UART test\r\n"); // MX generated USART3 init static void MX_USART3_UART_Init(void) { /* USER CODE BEGIN USART3_Init 0 */ /* USER CODE END USART3_Init 0 */ /* USER CODE BEGIN USART3_Init 1 */ /* USER CODE END USART3_Init 1 */ huart3.Instance = USART3; huart3.Init.BaudRate = 115200; huart3.Init.WordLength = UART_WORDLENGTH_8B; huart3.Init.StopBits = UART_STOPBITS_1; huart3.Init.Parity = UART_PARITY_NONE; huart3.Init.Mode = UART_MODE_TX_RX; huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; huart3.Init.OverSampling = UART_OVERSAMPLING_16; huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; if (HAL_UART

Hello,I am using the HRTIM on an STM32F334 to drive a buck/boost converter.I monitor MOSFET temperature using NTCs via ADC2, and I also need to measure the internal CPU temperature and VREFINT using ADC1.ADC configuration:ADC1Regular: VREFINT, TEMPSENSORInjected: VinADC2Regular: MosFetTemp1, MosFetTemp2, AnalogStartInfoInjected: VoutIssue:As soon as the HRTIM is initialized (even without starting it), the ADC regular conversion values become unstable.Observations:100 samples of VREFINT only → stable when HRTIM is not initialized100 samples of TEMPSENSOR only → stable when HRTIM is not initialized100 samples of (VREFINT + TEMPSENSOR) → stable when HRTIM is not initialized100 samples of (VREFINT + TEMPSENSOR + ANALOGSTARTINFO) → stable when HRTIM is not initializedAs soon as HRTIM is initialized, all these measurements become noisy/unstable.The issue is also present:even if HRTIM is not startedeven if GPIOs are not initialized  (so MOSFETs are not switching)even if line HAL_HRT

Hi everyone, I'm new to STM32 and I'm building an audio player. I'm using an SD card (via SPI) to feed audio data to a dac via I2S.The audio stutters and often plays the same 1-2 second snippets twice before moving on.I've tried implementing double buffering and i've checked the i2s configuration in circular mode.Code:https://github.com/darty555/stm32-i2s-dma.git

As asked in the subject: Is there a hole in the memory map of the STM32C552VC (Bank1 from 0x08000000 to 0x08020000 / Bank2 from 0x08040000 to 0x08060000) or are the two banks continuous from 0x08000000 to 0x08040000)

Hi Team,We are observing persistent and repeatable debug connectivity issues on multiple custom boards based on the STM32H745BIT6 MCU. These boards were initially functioning as expected; however, after repeated debug sessions, they started exhibiting failures. We request your support in identifying the potential root causes and guidance on recovery. We have performed Full Chip erase also whenever it was possible.  Below are our consolidated observations captured across multiple boards.Observed IssuesDebug Interface Failures After Multiple SessionsAfter several debug sessions, the following errors are observed intermittently:TARGET_HELD_UNDER_RESETTARGET_NOT_HALTEDTARGET_NO_DEVICEError: Unable to get core IDInconsistent Connectivity Between ToolsThe device intermittently connects using STM32CubeProgrammer.The same device frequently fails to connect in Debug mode using STM32CubeIDE.Loss of Debug Connection During RuntimeDuring debugging, the controller runs for a few seconds.T

I have a program where I have TIM2 CH1 set up in output compare mode. Approximately 0.5 ms after the timer is reset, CH1's compare value is reached. This triggers the CH1 DMA, which is a dummy DMA on DMA1 channel 1. The SPI TX DMA is synced to the TIM2_CH1 DMA (with a request count of 16, to allow 16 bytes through the SPI), and therefore if it is armed should automatically start at that moment. The purpose of this is to eventually provide an interrupt-free delay for an external SPI slave that requires a 350ns delay between CSn active and SCLK active.I have this all mostly working, but my problem is that about 5% of the time, the SPI DMA does not complete. I can't figure out what in my code is allowing this to happen. The basic structure is:Arm SPI DMAs.Reset TIM2 counter.Wait until the DMA completes. (This should be triggered by TIM2 reaching the compare value.However, for reasons I cannot understand, about 5-10% of my transfers never appear to start -- I wait for a long period of time

(HAL_SPI_Transmit_DMA works partially, HAL_DMA_Start_IT not working)I’m working with an STM32U5 MCU using SPI3 with GPDMA to drive an ILI9341 display. I’m trying to transmit a larger buffer (~23040 bytes), but display only receives about 1024 bytes, and goes into HAL_SPI_STATE_BUSY_TX forever.Function used: HAL_SPI_Transmit_DMA()Configs:  Thanks in advance !

My FMC clock, set to continuously generated, only cycles during a bus transaction.On my STM32N657I0H3Q, I have the following setup:FMC enabled in applicationChip Select NE1Muxed PSRAMData/Address: 16 bitsClock: Burst Read WriteAddressValid: YesWait: SynchronousThen, in the configuration, I have "CLK generated continuously" set. I have confirmed all of these settings in the resulting fmc.c code. I've also verified at runtime that hsram1.Instance->BTCR[FMC_NORSRAM_BANK1] = 0x183997(Where 1<<20 -- 0x1000000 is continuous clock generation).Meanwhile, my oscilloscope shows the FMC_CLK waveform:Clearly not continuous!