STM32H743IIK6: Some questions relating hardware design

[ELI_HAIT]

Hi,

During the design with the STM32H743IIK6 MCU few questions arise:

(1)  While designing a PCB with the STM32H743IIK6 (UFBGA176+25 package) with VDD=3.3V or 2.8V, I am unable to locate the VCCLDO pin, which is expected to be connected to external capacitor. Am i missing something in the pinout, or does the internal LDO in this specific package rely solely on the capacitors on the VCAP pins?

(2) There are two sets of QUADSPI I/O sets: BK1 and BK2 (i intend to use the BK2). However, I do not see any separate clock pins for each. Do both channels share the same QUADSPI_CLK signal for both banks?

(3) Regarding the USB interface: I see a VDD33USB pin, but there is no VDD5USB pin. Does this require an external 3.3V DC input, or is it an internal signal output that only requires a decoupling capacitor?
Additionally, I am unable to locate the USB_DP and USB_DM pins on the UFBGA176 package. Is there specific hardware documentation / example schema that clarifies the physical locations for the USB connection out of the MCU?

(4) Does the embedded ADC can operate in SE mode (without connecting the _N pins)?

 

Thanx,

Eli.

[TDK]

1) You mean VDDLDO? Per the datasheet: "When it is not available on a package, the VDDLDO pin is internally tied to VDD."

2) Yes

3) In the datasheet, "When it is not available on a package, the VDD50USB pin is internally tied to VDD33USB."

4) Yes

[ELI_HAIT]

Hi, TDK, 

Thank you for your responses and assistance. 

I’d like to double-check my understanding of the following:

(1) According to the datasheet, a capacitor should be connected between VDDLDO and GND - i assume it is required for LDO stability. However, in the 176+25UFBGA package this voltage remains internal and utilizes the capacitors connected to VCAP?

(2) When both VDD50USB and VDD33USB are routed to pins, is VDD50USB the input and VDD33USB an output which is internally generated from VDD50USB that requires a capacitor to GND?
But, if only VDD33USB is routed to a pin (without VDD50USB), the VDD33USB an input that should be connected externally to 3.3VDC?

(3) To interface the USB externally, is it sufficient to connect the OTG_FS_DP and OTG_FS_DM pins to the connector with only TVS protection or something else is required?

 

Thanx,

Eli.

 

[TDK]

1) The caps on VDDLDO and VCAP are for different rails, but they both stabilize voltage. If VDDLDO doesn't exist (is tied to VDD internally), it'll use the caps on VDD for stability.

2) Yes.

3) GND also needs connected. If the device is self-powered, VBUS needs connected and monitored. If the device is bus-powered, VBUS needs connected in order to obtain power.

 

[ELI_HAIT]

Hi, TDK, last question (i believe... :))

Decoupling caps for VDD:

BGA 0.65mm pitch allow to put only 0201 capacitors close to pins on the bottom side + bulk capacitors outside the BGA or in the unpopulated areas under it.

But there is an option to locate 0402 capacitors little bit farer from there.... additional few mm... in many other devices it is allowed.

Is there any application note about this - if the 0402 option is acceptable or i should use the 0201 capacitors?

[TDK]

0402 a few mm away will work fine. Look at the nucleo board for an example layout.

[PatrickF]

HI @ELI_HAIT 

worth to look to AN4938 Getting started with STM32H74xI/G and STM32H75xI/G MCU hardware development

Patrick

[ELI_HAIT]

Thanx

[TDK]

@ELI_HAIT Can you please mark the reply that helped you the most as the solution, rather than you own?

This helps other users find the answer to similar questions when they search or use the forum.