STM32 MCUs Products

Hi,I selected STM32H7A3ZIT6Q to use external SDRAM. However, in STM32CubeIDE under Connectivity → FMC, the SDRAM option is not available.When I select STM32H7A3ZIT6 (non-Q), the SDRAM option appears.Does the STM32H7A3ZIT6Q support SDRAM, or is this a CubeIDE limitation?Thanks.

Hey guys,I am searching for RoHS/REACH records for STM32G431KBU3/STM32G431KBU6 but they're only accessible for one of the STM32G431 parts.Any of you have any pointers to how I may else obtain such documentation?

SYS CONFIG =========================================== IO Supplys = 3,3V, VCORE = 2,5V regulator used, FSystem = 200 MHz Timer1 is configured for Output Compare CH1, sig 0.1MHz 50% duty expected (all necessary clk enabled) Compare SIG is routed to PK1 via alternate conf  __HAL_RCC_GPIOK_CLK_ENABLE(); GPIO_InitStruct.Pin = GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF1_TIM1; HAL_GPIO_Init(GPIOK, &GPIO_InitStruct); After exec of this routine, PK1(J15) pin is in floating mode (1V because of 2Meg external pull-up to supply) . Same signal routed to another port/same load with same routine is working properly  Same problem and behavior with TIM8 witch can use the same PK1 pin Note1 : if internal pull-up or pulldown added to pin conf, the pin is no longer floating, Hi(3,3V) for pull-up, Low(0,1V) for pulldown but still no signal output (input mode suppose

Hello everyone.  I am trying to build an i2c multi-drop network with STM32C0316CT6 targets. To achieve that i use the differential buffer PCA9615. Each target (and the master of course) has its own PCA9615, the topology is as shown in the picture below. My problem is that when clock stretch is enabled (default) and master pulls the clock low, then the target pulls the clock also low for a tiny amount of time during the normal pulse duration. PCA9615 i2c a-side (non-differential) sets the SCL (a-side) low to ~0.3V (as expected) and then the target pulls the SCL to 0V for that tiny amount of time. For that tiny amount of time, the master and the target are both holding the clock low. That results in an extra voltage offset on the differential side of the buffer. On the multi-drop network, all targets do the same and the differential voltage offset is multiplied and gets huge. The expected behaviour would be from the target to pull the line low only in the stretched pulse and not on

Hi,I am making updates to a custom PCB where I would like to add ADC functionality. My board is powered by batteries and I expect the supply voltage to fluctuate slightly and I need the ADC conversions to be accurate. The reference manual says I can use the internal Vrefint to calculate what the value of VDDA/VREF+ so that I may calculate my conversions with better accuracy. Additionally, I wanted to follow this guide (https://community.st.com/t5/stm32-mcus/how-to-use-the-stm32-adc-s-internal-reference-voltage/ta-p/621425) to understand how I may implement this in firmware.The issue I see now is that on the chip's datasheet it mentions that Vrefint is internally connected to ADC1_IN0, however, ADC1_IN0 has no pinout on this package of the chip. Furthermore, in STM32CubeMX the ADC1_IN0 channel is not able to be selected (although Vrefint channel is able to be selected).Now I have some confusion since the datasheet mentions the internal connection. Maybe this package does not have this a

We are using STM32G030C8T6 (LQFP48 package) in a new design and need clarification regarding pin 36: PA14‑BOOT0, which according to the datasheet serves both:SWCLK (Serial Wire Debug clock)BOOT0 (boot mode selection)In our earlier designs using similar STM32 devices, BOOT0 and SWCLK were separate pins. BOOT0 was typically pulled down, and SWCLK required no external pull.However, in the STM32G030 series, BOOT0 is multiplexed on PA14, which is also SWCLK. The datasheet states that upon reset, PA14 is configured as SWCLK with an internal pull‑down enabled.We would like clarity on the following points:Is an external pull‑down resistor required on PA14‑BOOT0, or is the internal pull‑down on PA14 sufficient for all conditions?Will adding an external pull‑down interfere with SWCLK operation during debugging?Are there recommended application notes or hardware guidelines specific to STM32G0‑series devices where BOOT0 is multiplexed with SWCLK?

Hello everyone, I'm having some trouble implementing I3C communication and would like to ask for some help. I am using the NUCLEO-H503RB board as my main controller. For the target devices, I have the NUCLEO-IKS01A3 expansion board and the TSC1641 (Click Board) connected. I'm currently facing some issues with the I3C communication setup between these components. I have successfully managed to read the WHO_AM_I ID from the LSM6DSO (on the NUCLEO-IKS01A3). However, when I attempt to read the ID from the TSC1641, the SCL line continues to output a clock signal (or stays toggling) without a proper response. I am seeking assistance in analyzing the root cause of this issue. 

Split from STM32G0B0: RM0454 link out-of-date ? - this is a new topic raising issues in the document itself.Hi @Amel NASRI ,Thank you for your quick answer.I have however encountered a few errors in that RM0454 Rev 5 that are different/fixed in RM0444 Rev 6. For example, the following is all done on an STM32G0B0CE (512kiB) rev Z.Erasing a flash page (page 78/989) PNB's limit should be 128 so it stays limited to the 256KiB of the selected bank using BKER. A higher value (for example 256+) errors the flash controller.If this is correct, the following image should also be incorrect (Table 9, pg 55/989)and be changed toAnother issue that I encountered is that the 512kiB STM32G0B0CE sometimes bricks when attempting to change the option byte DUAL_BANK (pg 81/989)I believe this should also be as in RM0444, 512kiB devices always operate in DUAL_BANK mode. Have I looked over something that caused me these issues? Or could you confirm that these are indeed errors in RM04

Hello, I have a nucleo board with STM32H563. I am trying to make a simple application that will take two ADC measurements with regular conversions. I've been going through the refference manual(RM0481 Rev4) and in the ADC overrun chapter on page 1072, It is stated that there is a three stage ADC_DR FIFO, but not much more about it is explained.  My question is: If i create a sequence of 2 channels and trigger them, would I be able to read the DR register twice with value of channel 1 and 2(with an assumption I am using channels 1 and 2), or will the value of channel 1 be overrun by channel 2 value immediately.I don't want to read the data in an ISR after one conversion is completed, I would liek to read them both together after they are both completed.And I don't need a workaround, I am trying to get to know what this ADC can really do. Thanks, Ivan

Hi I have been looking into the boot process for stm32n6 and was unclear about a few things. For booting from external flash the steps are as follows 1. build your app's bin file. The app should be built with the vector table at the start and the linker script should have a base address 0x341804002. Add the header using the signing tool3. Upload the code to flash using extloaderThis is correct right? The second step is what confuses me. I use the command STM32_SigningTool_CLI -bin Project.bin -nk -of 0x80000000 -t fsbl -o Project-trusted.bin -hv 2.3 -dump Project-trusted.binas indicated in https://github.com/STMicroelectronics/STM32CubeN6/tree/main/Projects/NUCLEO-N657X0-Q/Templates/Template. I did a hexdump on the generated Project-trusted.bin file and I have the following questions regarding it 1. The base header and padding header have a combined length of 576 bytes (0x240). After that the app starts. This doesn't line up with the linker script or UM323

Hi everyone, I am facing an issue with CAN communication on STM32F446ZCT6, where the CAN controller frequently enters the Bus-Off state. Hardware Details MCU: STM32F446ZCT6 CAN Transceiver: (TJA1042T) I am working with CAN communication on STM32F446ZCT6, and the CAN controller is frequently going into the Bus-Off state. I am using the HSI clock, configured from 8 MHz to 42 MHz, with the CAN clock derived from APB1 = 42 MHz I have enabled Auto Bus-Off Management and tested multiple bitrates (500 kbps, 250 kbps, and 125 kbps), but the issue still occurs. I see bit errors and acknowledgment errors, which eventually cause Bus-Off.Can you please help me to solve this issue.

I am working on STM32h747 series. I am debugging both CM4 and CM7. After a while, CM4 stops responding and the debug messages shows:"Error in final launch sequence: Failed to start GDB serverFailed to start GDB serverError in initializing ST-LINK device.Reason: (4) No device found on target." If I run CM7 independently, it works but CM4 is not responding. I tried to erase the entire board but CM4 is still not responding and the same message is appearing.

Hello, I need to have D-Cache enabled to improve performance of FMC external SDRAM (it's >3x slower without D-Cache enabled). I also want to use I2S for audio. But with D-Cache enabled, I don't get any data from ADC. What can I do to use I2S with D-Cache enabled?

Hi.  I have a newly purchased NUCLEO-U575ZI-Q.  I followed the instructions here to install the toolchain on Windows 11:https://www.st.com/en/evaluation-tools/nucleo-u575zi-q.html#documentationhttps://wiki.st.com/stm32mcu/wiki/STM32StepByStep:Step1_Tools_installationAfter one unsuccessful attempt where I chose my own installation folders, I uninstalled everything and took the defaults.What a mess!  The default installation folders are spread between AppData, Program Files, and C:\ST.  But OK, if that's what it takes.Unfortunately, I got to step 5 and found that the instructions diverge from reality.They never said to click Finish to complete the Import Projects dialog.  And there is no way to select the project they mention from it.  But if I click Finish, then a tiny icon appears on the upper left.  If I click it, then there is a Project Explorer window.The next step is:My IDE has no Debug icon (the the little yellow blob on its lower left).  Bu

Continuation of this thread. Hello,  I've wired SDRAM (AS4C4M16SA-5TCN)  with STM32H730ZBT. Connection works, I can read/write data, but every other byte.  Let's start with array declaration: uint8_t *externalRAM = (uint8_t*)0xC0000000; /* USER CODE END PV */ Then I'm trying to write some bytes to this array, ie: externalRAM[0] = 0xAA; externalRAM[1] = 0xAA; externalRAM[2] = 0xAA; externalRAM[3] = 0xAA;   And to read it: uint8_t test[4]; test[0] = externalRAM[0]; test[1] = externalRAM[1]; test[2] = externalRAM[2]; test[3] = externalRAM[3]; And this is the result: Sometimes test[1] has 0xAA too, but mostly it's 0. I've tried to lower FMC frequency or change memory timings. What does this look like?

Hello,I'm spec'ing a system where we would need to interface 4x eight-channel ADCs with an MCU for audio capture. Simultaneous capture on all channels is an important requirement.Currently we are considering the STM32H750VB MCU which has 4x SAI interfaces, and the Analog Devices AD7768. All ADCs would be running at the same time, synchronized, and the data from them would be DMAed into ring buffers.I'm not familiar with the ST SAI interface. It seems like they can support 8 channels in TDM mode (which that ADC supports), but I'm not sure?Can this be done with the STM32H750VB?

Hi Team,We I have shortlisted the STM32U535RET6QTR microcontroller for our microwave oven control panel. The MCU includes an integrated Touch Sensing Controller (TSC), and our design requires 8 capacitive touch keys.Before finalizing the component selection, we require clarification on the following points to ensure compliance with home‑appliance safety and EMC standards:1.Is the STM32U535RET6QTR suitable for microwave‑oven capacitive‑touch applications?2.Does ST provide any dedicated capacitive‑touch sensing IC, apart from the built‑in TSC in STM32 MCUs?3.What are the advantages of using STM32U535RET6QTR (with integrated TSC) compared to a dedicated touch‑sensing chip?4.If we use the integrated TSC in STM32U535RET6QTR, what hardware challenges may occur?5.What software‑related challenges can arise with the integrated TSC?6.Can STM32U535RET6QTR meet home‑appliance certification requirements such asIEC 60335‑1 / IEC 60730‑1 Class‑B?7.For an 8‑key capacitive touch panel, what does ST rec

G'day Brains Trust,Does anyone know where ST record the export classification for their products?Specifically looking for the ECCN for STM32G474RET3.RegardsGTC-BH

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I am developing a Battery Management System (BMS) for a hybrid inverter solar panel system. I am using the ADBMS1818 IC as the battery management chip from Analog Devices. Currently, I am looking for a suitable MCU for my system. I found that the CYT2B7 MCU from Cypress Infineon fits my system well. However, during the development process, I need to use an MCU from STMicroelectronics. Could you recommend a series that meets my needs? Below are the specifications of the CYT2B7 Thank you for your assistance.

I tried to use the internal watchdog IWDG and WWDG) on an STM32L433It worked fine until the device went into low power modes, standby and shutdown.Because the watchdogs still runs during low power modes, but as the prcoessor is not running the watchdog times out and keeps resetting the processor.So then I looked at using an external watchdog (STWD100) which can be disabled when in low power mode.  I wrote a post about the topic here...https://community.st.com/t5/others-stm32-mcus-related/how-to-interface-external-watchdog-stwd100-with-stm32/m-p/879006#M9433But a comment was made that "If you can enable and disable the watchdog, wild-running code can as well, and you cannot really rely on the watchdog"So how should a watchdog (internal or external) be handled in low power modes ?Surely you dont want to keep waking the processor every few milliseconds just to reset the watchdog timer, as the defies the point of being in low power mode to save battery power ?I was told that

Hi everyone,I think I’ve messed up my NUCLEO-H755ZIQ board. A few days ago, I accidentally unplugged the board while an active debug session was running. Since then, the board "dies" every time I power it off.To get it back to a working state, I have to follow this tedious process every single time:Set Boot0 to VCC.Connect via STM32CubeProgrammer (Power Down mode).Perform a Full Mass Erase.Disconnect and set Boot0 back to GND.Connect again and flash a simple .elf file (a basic SPI project that toggles an LED) just to verify it's alive.After this, I can debug normally in CubeIDE—until I power cycle the board again.This was manageable until I started working on a Bootloader project. Today, it took me all morning to recover the board because the bootloader logic seems to interfere with my "recovery" steps.I’ve already tried messing with Option Bytes and performing several mass erases, but the issue persists. It feels like the flash or the option bytes are stuck in a state that prevents a

I’m working on an STM32H7R7 project using SDMMC1 + FreeRTOS (CMSIS-RTOS v2) + FatFs, all generated with STM32CubeMX.I’m facing an issue where f_mount(opt=0) works, but the system blocks inside f_open() and never returns, so the return value cannot be checked.A key aspect of the problem is that the behavior depends on how the device is started:After flashing the firmware with a debugger connected and running immediately, the system behaves differently.After a cold power-up (power removed and re-applied, no debugger connected), the same binary consistently freezes when reaching f_open().In both cases:The code is identicalThe clock configuration and FreeRTOS setup are unchangedNo additional initialization is performed when the debugger is attachedThis suggests a timing-, initialization-, or peripheral-state-related issue that manifests only on a true power-on reset and not after a debugger-initiated reset.Additional observations:f_mount(&SDFatFs, "0:", 1) initially caused a block, but

STM32F401 (Blackpill) – 2.4s Drift in 30 Minutes Between Two Identical Boards Using TIM2 (HSI Clock)I am working on time synchronization between two identical Blackpill STM32F401CCU6 boards.Both boards:Use internal HSI oscillatorSame firmwareSame clock configurationTIM2 configured as 1 MHz free-running counter (1 µs resolution)32-bit counter (auto-reload = 0xFFFFFFFF)Clock configuration:HSI ONPLL enabled (HSI → PLL → SYSCLK)SYSCLK = 32 MHzTIM2 prescaler = 31 → 1 MHz timer tickInitializationBoth boards started in STANDALONE modeBoth boards waited for button interruptThe board which gets interrupt became MASTERSynchronization MethodOne board acts as MASTEROther board acts as SLAVECommunication via UART (115200 baud)Master sends a 5-byte sync packet:0xAA + 4-byte counter valueSlave receives and sets:htim2.Instance->CNT = received_counter; UART disabled and connection removedInitial sync works correctly.ProblemAfter synchronization:Drift increases over timeAfter 30 minutes → ~2400 ms di

HiI am drawing a PCBA with STM32H7R3V8H6 but for the USB HS interface PHY its not clear which pins are USB differential D+ and D- data pins?krØystein