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SKarl.3
Associate II
September 19, 2024
Question

SAI for 8 channel TDM?

  • September 19, 2024
  • 7 replies
  • 4741 views

Hello,

I'm spec'ing a system where we would need to interface 4x eight-channel ADCs with an MCU for audio capture. Simultaneous capture on all channels is an important requirement.

Currently we are considering the STM32H750VB MCU which has 4x SAI interfaces, and the Analog Devices AD7768. All ADCs would be running at the same time, synchronized, and the data from them would be DMAed into ring buffers.

I'm not familiar with the ST SAI interface. It seems like they can support 8 channels in TDM mode (which that ADC supports), but I'm not sure?

Can this be done with the STM32H750VB?

7 replies

Andrew Neil
Super User
September 19, 2024

@SKarl.3 wrote:

I'm not familiar with the ST SAI interface. ?


Neither am I, but does this help: https://www.st.com/resource/en/product_training/STM32F7_Peripheral_SAI.pdf ?

A complex system that works is invariably found to have evolved from a simple system that worked.A complex system designed from scratch never works and cannot be patched up to make it work.
LCE
Principal II
September 19, 2024

I know the H723 / H735 SAI a little bit better now - at least for normal "stereo" ADCs / DACs / SPDIF TX, but I have not used TDM.

There is the SAI's SLOTR register where you can set up to 16 "slots" per SAI block and enable each slot individually, so at first glance it looks feasible.

Check also the reference manual! This uses "TDM" mostly in regard to PDM microphones.

Depending on the sampling rate, I wonder how you will cope with these amounts of data?
At fs = 50 kHz, that would be ~1.6 Msamples/s, which should not be a problem for the DMA / internal RAM (check if that particular H7 supports HyperRAM via its OCTOSPI, some are kinda whacky), but I guess DSP stuff will be too much.

SKarl.3
SKarl.3Author
Associate II
September 19, 2024

Thanks. I saw that and it does look like it is possible. Just looking for more verification.

The application is beam forming, and I'm hoping to sample at up to 192kHz if possible, for maximum time resolution. Data would just get dumped into ring buffers. Any DSP would be done on a few highly decimated streams. I know this is getting into territory that might be more suitable for a small FPGA, but I'd like to stick with an MCU if possible.

 

AScha.3
Super User
September 19, 2024

Hi,

>Can this be done with the STM32H750VB?

Maybe...

1. i would not choose the cheapest H7 , better STM32H723 or H733 (i use H743ZIT or H753ZIT ).

-> H723 : about 500K ram, 1M flash, at 550MHz; H750 with only 128K flash -> only small program or external spi-flash (some extra game to play.)

2. check (just in Cube) that you can use all pins you want/need, maybe need more pins. just check before buy.

3. "TDM" is not same for AD and STM ... (TDM on STM is for the digital mics);

your ADC has data like this (from ds):

 

AScha3_0-1726770324589.png

This is not I2S, which is "standard" for audio and also on SAI works fine; you need to select "free" PCM format,

but on this you only could choose 32bit/ch , to get this special format in the SAI slots; maybe like this:

AScha3_1-1726771415096.png

-> for mode 11 on ADC, all 8ch on one data line.

(But i am not sure, this setting is working - i never tried something "strange" like this , so you have to test it yourself. And i will not work on first try - except your very lucky. )

e.g. "frame synchro" lo or hi here the right one - i dont know. (read manuals...or just try...)

 

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LCE
Principal II
September 20, 2024

Do NOT use the H723 .. H735:

these have "only" 2 SAIs (with 2 blocks each -> 4 stereo ADCs without TDM),
but the biggest restriction is that SAI 4 is in "domain 3" and can only be accesses via the slightly different BDMA (not DMA1 / 2), which again cannot access external RAM - which you will surely need at 25 Mbyte / s.

How do you want to transmit data?

PS: I'm running 8 ADC channels 32bit / 200kHz (only 6.4 Mbyte/s) with H723 .. H735 and OCTOSPI / HyperRAM (100MHz DDR),  Ethernet (self-made driver + lwIP), no RTOS, using as much DMA as possible.
CPU at 400 MHz is idle about 50% of the time.

In hindsight, I would have been faster with development with an FPGA - mainly due to more experience with FPGAs than with STM32 - and some problems / bad surprises on the STM32 side (SAI 4 / DMA no HyperRam access).

SKarl.3
SKarl.3Author
Associate II
September 20, 2024

This was super informative. Thanks so much!

Explorer II
February 18, 2026

hey , did you figure it out , I found my self in same situation trying to design with stm32h743 and ads1278 with up to 24channel daisy chained and i don't know if I can get it to work either with SPI or SAI

Explorer II
February 18, 2026

I've used the ADS1278 with an H743 (and H723) SAI but it was only a single one, and at half your rate. 

Potential roadblocks:

1) NBSLOT is limited to 16(-1), which will probably get in the way of your 24-channel daisy-chain. [Ref RM0468 r3 Sec  56.6.8]

2) In High-Speed mode (>52ksps) the best you can do is 10 channels on DOUT1 [Ref datasheet (SBAS367F) Table 15].

I suspect you'll want at least 3x SAIs (no daisy-chaining) on whatever STM32 you pick. You can still sync them with /SYNC.

Explorer II
February 18, 2026

Thank you very much that was very helpful , would you mind sharing any source code or repos for your prior application with the ads1278 and h743 , can I use only two SAI , SAI1 ( with two both blocks) and SAI2, would it be better than raw spi and write my own tdm and parsing code ?  

Explorer II
February 19, 2026

The code is owned by someone else, so I can't publish it. I think I can say that the SAI setup, including MCLK, DMA, and ISRs, is less than 100 lines of code (no HAL).

You could (I think) do everything the SAI is doing, but the SAI will do it more simply and reliably. Once started, it runs itself and periodically presents blocks of (isochronous) data.

I expect you could use the SAI A and B sides as 2x SAIs, though I haven't tried it.