STM32H563 ADC_DR FIFO clarification

[Quo]

Hello,

 

I have a nucleo board with STM32H563. I am trying to make a simple application that will take two ADC measurements with regular conversions. I've been going through the refference manual(RM0481 Rev4) and in the ADC overrun chapter on page 1072, It is stated that there is a three stage ADC_DR FIFO, but not much more about it is explained. 

 

My question is: If i create a sequence of 2 channels and trigger them, would I be able to read the DR register twice with value of channel 1 and 2(with an assumption I am using channels 1 and 2), or will the value of channel 1 be overrun by channel 2 value immediately.

I don't want to read the data in an ISR after one conversion is completed, I would liek to read them both together after they are both completed.

And I don't need a workaround, I am trying to get to know what this ADC can really do.

 

Thanks, Ivan

[mƎALLEm]

Hello,

According to this description from the reference manual :

So if you configure the STM32H563 ADC with OVRMOD = 0 (FIFO enabled), and perform a sequence of two regular conversions, you can read the ADC_DR register twice to obtain both results in order. The FIFO ensures that both values are retained until you read them, as long as you do not exceed the three-stage depth.