STM32 MCUs Products

I have followed the datasheets and tried to calculate my reference voltage. I am supplying steady 3V on Vref+ pin but I wanted to confirm this because I have some troubles with the ADC precision.So I read the internal voltage both on my card and on a nucelo-C092rc. This is my results: My board:Vref+ = 3.0 * 1659 / 1805 = 2.755Nucelo board:Vref+ = 3.0 * 1665 / 1641 = 3.043However I am quite certain that the nucelo boards are using 3.3 V as reference and my board are using 3 V as reference.So if I swap the 3.0 V from the datasheet into 3.3 V I get the following:My board:Vref+ = 3.3 * 1659 / 1805 = 3.033Nucelo board:Vref+ = 3.3 * 1665 / 1641 = 3.348Which match more my expectations, can someone confirm or deny this typo?I add my adc init function:u16 uiDelay = 0; ADC_CFGR2.CKMODE = 0x0; // Clock mode set to ADCCLK ADC_CCR.PRESC = 0x2; // ADC prescaler set to 48MHz / 4 = 12MHz ADC_CFGR1.RES = 0x0; // Set 12 bit resolution ADC_SMPR = 0x07; // Sampling time set to 1,5 ADC clock cyc

Hi everyone,We are encountering a XSPI Deadlock on our STM32H7S7-Discovery board (STM32H7S78-DK).To provide some context, our system is configured as follows:External FLASH: Connected to XSPI1. Swapped through XSPIM to port 2 and operates in memory mapped mode. MCE1 is activated across the entire address range using the AES-STREAM Cipher.External PSRAM: Connected to XSPI2. Swapped through XSPIM to port 1 and operates in memory mapped mode. MCE2 is activated across the entire address range using the NOEKEON-BLOCK Cipher.The issue occurs when running an LZO decompression algorithm. The algorithm reads compressed data from the PSRAM and writes the decompressed output back to the PSRAM, while the code is being executed on External FLASH.At some point during decompression, the core completely freezes, no HardFault or BusFault is triggered, and the debugger permanently loses its connection to the core.We have tried multiple approaches to resolve, including the official er

Hello,I came across the following problem: whenever firmware writes some data to flash memory, the NRST pin doesn't work. I mean, when low level is asserted on NRST pin the device starts to run software not at 0x0800... address but at 0x1FFF.... The same happens in the debugger: when I press "Reset the chip..." button. I get the message: "Break at address "0x1fff5236" with no debug information available, or outside of program code."The data is written to flash memory page which is  not used by the running program code. Data is correctly written and no error is shown in the FLASH->SR register. I didn't change any option bytes. The device runs at 80 MHz, BOOT0 pin is grounded. What am I doing wrong ?

I am using STM32G0B1KCT6 MCU, i would like to use the full flash of 256KB starting from 0x8000000 to 0x803FFFF. but am unable to flash in bank 2 (ranging from 0x8020000 to 0x803FFFF).if i reduce the flash size to Bank1 only, then am able to flash and run the code.I am aware its default dual bank MCU. PFA code snippet for changing it to single bank.Also tried changing it single bank using the stcubeprogrammer but still fails to flash the MCU.   void ConfigureFlashToSingleBank(void) { FLASH_OBProgramInitTypeDef OBInit; HAL_FLASHEx_OBGetConfig(&OBInit); /* Check if Dual Bank mode is enabled */ if (OBInit.USERConfig & FLASH_OPTR_DUAL_BANK) { HAL_FLASH_Unlock(); HAL_FLASH_OB_Unlock(); OBInit.OptionType = OPTIONBYTE_USER; /* Disable Dual Bank (enable linear 256KB flash) */ OBInit.USERConfig &= ~FLASH_OPTR_DUAL_BANK; if (HAL_FLASHEx_OBProgram(&OBInit) == HAL_OK) { HAL_FLASH_OB_Launch(); // triggers reset } HAL_FLASH_OB_Lock(); HAL_FLASH_Loc

HiI need help in erasing the device: STM32H735IGK3, This device is getting erased only till sector 0.There were total 8 sectors.I am following the steps given in  Reference manual for erase operation but still it didn't work.Could you please suggest something to resolve this issue with Erase?Or please point out the reason which is throwing this issue.Thanks!Saista 

Hi,I have a DMA2D issue with a STM32N6 Nucleo-144 board. I can use the DMA2D to blend two framebuffers if the inputs are in the AXISRAM1. However, when one of the framebuffers is in AXISRAM3 (NPU RAM), the DMA2D doesn't copy from the relevant framebuffer. There is no error, but the output is invalid.I can copy to the AXISRAM3 using HPDMA without any issue. I have configured the RISAF4/5/6; otherwise, I am unable to copy to AXISRAM3. This is the code to configure RISAF4/5/6 (NPU RAMs): __HAL_RCC_RISAF_CLK_ENABLE(); RISAF4->REG[0].CFGR = 0x00000000; RISAF4->REG[1].CFGR = 0x00000000; RISAF4->REG[0].CIDCFGR = 0x000F000F; /* RW for everyone */ RISAF4->REG[0].ENDR = 0xFFFFFFFF; /* all-encompassing */ RISAF4->REG[0].CFGR = 0x00000101; /* enabled, secure, unprivileged for everyone */ RISAF4->REG[1].CIDCFGR = 0x00FF00FF; /* RW for everyone */ RISAF4->REG[1].ENDR = 0xFFFFFFFF; /* all-encompassing */ RISAF4->REG[1].CFGR = 0x00000001; /* enabled, non-secu

I am working on a new design using the using the STM32H753XIH6.  The microcontroller has 1Mbyte of RAM onboard.  The software requirement calls for 4Mbyte of RAM.  I plan to add 4Mbyte of SRAM using the FMC parallel bus.  How does the STM32H753 handle the transition from onboard RAM to off chip RAM data?  Any tips or recommendations for implementing the design?I have also wondered how this same situation would be handled with the FLASH portion of the memory, but that might call for another thread to be started for that answer.Thank you

Greetingwhat want to achiveThe current state.What we have tried.Hey there Community,We are running a project were we need to interface with an AP memory on a custom made board. We intend on using the PSRAM for image capture for a 5mpx image dumped by the dcmipp peripheral. To test the PSRAM separately, we came up with a test to confirm that we get no errors while interacting with it.We are failing to communicate with the memory at frequencies higher than 100Mhz, and seeing a large number of errors at 100Mhz and zero errors at 50Mhz. This is a big hinderance because the memory should be able to be set all the way to 250Mhz and we do also see these errors appear in the images taken.We have attached the specifications we are working with as well as the configurations we are using.SpecificationsSTM32N657X0HxQAPS256XXN-OBx9XSPI interface (x16) (xspi1)Other SpecificationsMemory mapped modeSchematic similar to the STM32N6 DK.Below are the materials used to aid with the configuration

Hello fellow STM32 users.Only after making a prototype where I use PC13 for calibrating the RTC, I stumbled upon the PC13 issue. Or maybe I had seen it before, and forgotten about it.For those unfamiliar with this issue, using PC13 for anything I/O related may affect the RTC clock frequency, in case you use an external RTC crystal (LSE oscillator). This is copied from the STM32G4 errata sheet:But how bad can it be, really? After (re)discovering this, I decided to put it to the test. I made a firmware version where I could select which I/O port to use for calibration. I use the 1 Hz calibration output, and have a frequency counter measure the average pulse period over 32 consecutive pulses. The frequency counter uses an external GPSDO as frequency reference, so the result should be pretty accurate.Using PC13 for the 1 Hz calibration signal, I measured a 243.7 ppm deviation. Pretty big, actually, but still possible to compensate for in the RTC_CALR register.However, when I used PB2 for t

#CAN​  #Example​ #STM32CubeMX​

TX works but RX interrupt not triggered Hello,I am currently using a custom board based on STM32H563ZIT6. My goal is to establish communication over RS485 between the STM32 and a PC (using Hterm). The system is designed to receive a command and send a response.Communication Details:Interface: RS485 (half-duplex)PC Tool: HtermConverter: USB COM 485 PLUS 4Packet size: Very small (typically 4 bytes)Transmission interval: ≥ 300 msCurrent Situation:Communication works perfectly between 115200 and 2,000,000 baudI am trying to increase the baud rate up to 12 MbaudProblem:At 12 Mbaud:STM32 → PC communication works correctly(I can see transmitted data on Hterm)PC → STM32 communication does NOT workSTM32 does not receive any dataRX interrupt is not triggered at allIt behaves as if no data is arrivingAdditional Notes:I have checked the termination resistor, and it seems correctThe data sent from PC is valid (verified from Hterm)UART baud rate is configured up to 12.5 Mbaud in CubeMXThe issue

Hello St community !for now i'm trying to build a project based on the nucelo-N675-Q board. I'm trying to interface an STEVAL-66GYMAI1 camera and plot 2 frames values into the terminal . I'm building my project based on this repo https://github.com/supungamlath/STM32N6_Survivor_Detection . I made sure to copy the middlewares for my specific sensor but i'm finding that the camera camera never streaming a real data based on the debugging and getting an callback error on line 1 I'm attaching my project zip file so can anyone help get through this problem !Thank you ! 

Hi, Planning to use VFQFPN68 package. I am confused about the max core clock I can use. CubeMx shows 550MHz for every "Power Regulator Voltage Scale (0-3)".I remember reading VFQFPN68 has only DCDC solution so max core clock is 400MHz Can anyone explain please?Thanks,Tim 

Hi ST community,I’m working with an STM32H563 MCU and trying to use the pin labeled JTDO/TRACESWO as UART7_RX because the datasheet/alternate function table shows that this pin supports UART7_RX. However, UART transmission works correctly, but UART reception does not work when using this pin. If I switch to a different pin, both TX and RX function as expected.Here’s what I’ve checked so far:Configured the pin in STM32CubeMX as UART7_RX (alternate function mode)Verified UART7 peripheral initialization is correctChecked baud rate and UART settingsConfirmed hardware wiring:External TX connected to STM32 UART7_RXCommon GND connectedSignal level is 3.3VTried disabling trace/SWO in CubeMX by setting by debug to “Serial Wire” instead of trace modeAlso tested with debugger disconnected after programmingMy question:Is the JTDO/TRACESWO pin fully usable as UART7_RX on STM32H5, or is it reserved/limited due to debug trace functionality?Is there any additional register/configuration needed to

Hello, I've just received my custom PCB with an STM32H743VIT6 MCU. It has a Samsung eMMC connected to the SDMMC1 interface (MMC 8 Bits Wide Bus) : (I'll link the eMMC datasheet below.) I'm encountering some issues while initializing the device with the MX_SDMMC1_MMC_Init function. More particularly it seems to be stuck in the HAL_MMC_InitCard function, on this block :  /* Card initialization */ errorstate = MMC_InitCard(hmmc); if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->State = HAL_MMC_STATE_READY; hmmc->ErrorCode |= errorstate; return HAL_ERROR; }   When i launch a debug session it seems to freeze on this block : /* Get CSD parameters */ if (HAL_MMC_GetCardCSD(hmmc, &CSD) != HAL_OK) { return hmmc->ErrorCode; }   Here's the variables states at this breakpoint : The data does not seem coherent. Am I missing something here ?For the configuration of the SDMMC1 interface i setted the Clock at 50MHz on the Clock Configuration, an

I have a question regarding an F407 wake-up error. I am using an F407ZGT and have connected the power switch to PA0 using a pull-down resistor. HAL_SuspendTick(); HAL_PWR_EnableWakeUpPin( PWR_WAKEUP_PIN1 ); __HAL_PWR_CLEAR_FLAG( PWR_FLAG_WU | PWR_FLAG_SB ); HAL_PWR_EnterSTANDBYMode(); I have been using this code successfully. However, after modifying the firmware and downloading it, or when downloading via the gang tool, the MCU fails to wake up via the wake-up input—though not always. Once this issue occurs on a board, the wake-up function permanently stops working, regardless of any operations performed. Is there any way to restore the wake-up function? Please help me!

This is in relation to post "Strange behavior with STM32G474QE pin PB4(Solved: Re: Strange behaviour with STM32G474QE pin PB4 - STMicroelectronics Community)" I'm facing the issue of PB4 going high for 27ms approx after MCU reset. My design is freezed, And this pin is connected to a relay which turns ON when this pin goes high. The relay turn on time is 7.5ms. Is there a solution in code initialization so that this pulse stays below 7.5ms. I'm attaching the waveform. 

I am new to using stm32 MCUs and I was following a youtube tutorial on how to set up a debugger for dual core MCUs. Before changing some settings I was able to start the debugger without any errors. Now when I try to run the debugger I get this error window popup:'Launching file_CM4 Debug' has encountered a problem. Error in final launch sequence:Failed to start GDB server When I click on details I get:Error in final launch sequence:Failed to start GDB serverFailed to start GDB serverError in initializing ST-LINK device.Reason: (4) No device found on target. I also noticed that when I plug the controller in the USB port and open NOD_H755ZIQ in This PC, it has 4 files (it had 3 files before). New file is called FAIL.TXT and it says: The interface firmware FAILED to reset/halt the target MCU This is the youtube tutorial that I followed : https://www.youtube.com/watch?v=jI1k6p-fduE Can anyone help me with this?Is it possible to fix this problem or do I n

Hi,On the stm32c5 nucleo board (NUCLEO-C5A3ZG) there is T1S OA PMD driver (not mounted?).  In the header file "stm32c593xx.h" exists a 10BASE-T1S control register "MAC10BT1SCR". But there is no documentation in the Reference Manual RM0522 Rev 1, and I can't find a way to enable T1S on MXcube2.Can anyone help me here? Is the T1S PDM really integrated in the C5 series?I would really like to experiment with 10Base T1S.RegardsPatrick

Hi, I need to use a 5V external clock for an stm32g473. The datasheet in table 39. High-speed external user clock characteristics says Vhsel is max Vdd, but Table 12. STM32G473xB/xC/xE pin definition says PF0 / OSC_IN is FT_a (five volt tolerant). Is it safe to use an external 5V clock ? Thx, 

Ok, this is perhaps esoteric, so maybe there is some research out there.   I am looking at STM32U3 or STM32C5, but the problem applies to pretty much all CM33 based ST MCUs.  The bus matrix implies a fast multiplexor for GPDMA (and SDMMC) to SRAM1. So unless dealing with burst transfers to SRAM (yes, SDMMC does that, and the GPDMA channels with the 32 byte FIFO could do that if the transfer is a multiple of 4 bytes), this fast multiplexor seems to save 1 clock reducing a beat to 2 clocks (if somebody has details for AHB vs. APB, that would be interesting). So to minimize latency and maximize bandwidth, DMA buffers (.dma section) should go into SRAM1.    So if DMA goes into SRAM1, then should not all the stacks go into SRAM2 ? I would assume burst DMA to/from SRAM1 would introduce some additional latency, especially in the way for ISR stacking / unstacking. Is this just overthinking this, or is that measurable ?   Now some U3 parts have SRAM3. One thought is to

I am currently working on the STM32N6570-DK board and need guidance on FSBL configuration, multi-layer project structure, and external flash programming.Issue 1: FSBL Peripheral ConfigurationI enabled multiple peripherals in FSBL:USART1, I2CBSPXSPI1, XSPI2CSI, DCMIPPVENC, JPEGAfter enabling these, I am getting an "unsupported relocation" error.Kindly guide:Which peripherals are recommended to enable in FSBLWhich peripherals should be initialized in the Application layer insteadProper distribution of initialization between:FSBLApplicationExternal Memory LoaderIssue 2: Multi-Layer Project UnderstandingCurrently, the project has:Three separate layers (FSBL, Application, External Loader)Each has its own startup file and main functionI would like to understand:How these three layers work togetherExecution flow between FSBL → ApplicationHow memory mapping and control transfer happenThere are three separate build outputs—which one should be flashed?How will all three sections work together in

I would like to connect a 12-bit ADC operating at 10MSps to the PSSI interface of the STM32N657 device.  There is some confusion as to the nature of the clock source. The reference manual indicates that this may be either an input or an output.  If configured as an output, what is the source of the clock?  Examples suggest that a PWM timer needs to be used.  Here is an illustration of what I would like to do:Do I need to use the PWM timer as the clock source?

I'm using LPTIM1 in encoder mode and have noticed that, if there's jitter on one of the encoder signals the count will gradually creep up which should not be possible in encoder mode.This is on a decent encoder that's got an RC network (per the Bourns data sheet / appnote) in front of it too so this isn't nasty HF noise, it's good solid pulses of 50-100ms or more on one channel but the counter seems to creep up.Identical encoders wired to TIM2 / TIM3 behave normally, and my colleague has seen the same issue in another project using the same setup - LPTIM has a problem where TIMx does not.Init code for LPTIM1:/* LPTIM1 init function */ void MX_LPTIM1_Init(void) { /* USER CODE BEGIN LPTIM1_Init 0 */ /* USER CODE END LPTIM1_Init 0 */ LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1); /* Peripheral clock enable */ LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPTIM1); LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOB); /**LPTIM1 GPIO

I started getting this message when I try to debug my code. However, there are currently no breakpoints in my code at all. I have gotten this in the past and I deleted and redownloaded the IDE which I really do not want to do again. I am running it on Mac. Any suggestions are helpful.// Simple ADC Reader // ADC1_1 on PA1 // Port A on AHB1 // ADC on APB2   #include "stm32f4xx.h" #include "printUSART.h"   int val = 0;   int main(void){   USART2_Init();   RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;   GPIOA->MODER = GPIO_MODER_MODE0_0 | GPIO_MODER_MODE0_1;   RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;   ADC1->CR2 = 0;   ADC1->SQR3 |= ADC_SQR3_SQ1_0;   ADC1->CR2 |= ADC_CR2_ADON;   while(1){ ADC1->CR2 |= ADC_CR2_SWSTART; while(!(ADC1->SR & ADC_SR_EOC)){} val = ADC1->DR; printf("\n%d", val);   }   }