STM32 MCUs Products

HI~I use STM32H563ZI NUCLEO.And I develpe LPUART GPDMA , but  LPUART GPDMA2 rx interrupt not working.LPUART RX GPDMA ch0LPUART TX GPDMA ch1Let me know how to config. Thanks

Title edited to give an accurate idea of the issue. Hello together, i had a problem with setting a correct bit time on a CAN-port. On my nucleo-h755ZI-Q board, I want to operate the FDCAN1 by the CM4 in classic-can mode with a baud rate of 1 MHz. I supply the FDCAN with a clock of 50MHz: Therefore the corresponding registers are set as follows: With: this excerpt in the reference manual, the calculation is: tfdcan_tq_ck = 0,02 µs  <- (1/50MHz) tq = 0,1µs          <-             (0,02 *  5) The bit time ist 1µs   <-  (0,1 *( 7+1+0+1+1)) -> baudrate is 1 Mhz    -> 1/1µs But in the outgoing frames, I measure a bit time of approx. 3µs. Enlarged: How can that be? What did I do wrong or overlook? Thank you and best regards, HiST    

We would like to connect LCD panel with parallel 8080 type LCD interface.  The pin can be setup as follows.  LCD_CS --- FMC_NE1  LCD_RD --- FMC_NOE  LCD_RW --- FMC_NWE  LCD_ReadResistor  -- FMC_A16  LCD_D[0:15]  --- FMC_D[0:15]/AD[0:15]If the FMC_A16 set for LCD register select, I think we don't need to use multiplexed mode.Also Cube IDE seems have "LCD interface" as Memory Type on FMC configuration. But, on the other hand, the note for FMC on the datasheet (17page DS14258 Rev5) say"2. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 chip select." So, I'm confused for now.Can we use 16-bit parallel LCD interface on FMC with STM32H563VIT6 LQFP100 package?And, if we can use "LCD interface" memory type on FMC configuration, is there any specific care needed?  

himy Hex file have a  90kB .text session size,and I want to flash it into stm32G474cbtx mcu which have 128kb dual bank flash. I use stm32cubeProgrammer v2.19.0 and stm32CubeIDE v1.19.0. if the option byte DBANK is 1,  I can successfully flash it using stm32cubeProgrammer, but fail  to flash it usingstm32CubeIDE when I start debug session. The error mesage is "operation exceeds memory limits". if the option byte is 0, then both tools can flash successfully. I know when DANK is 1,  stm32g474cbtx 's two bank address is not continuous, so I think in this case, both tools should fail to flash,but why stm32cubeProgrammer can succussfully flash it (and the program runs normmally) ?  

Hi All. So, I'm currently working on a project that I need some assistance with... I'm using the HRTimer and ADC. Timer A and Timer E both control my gate drive outputs; they're variable frequency. I also have Timer F, which controls my ADC sampling. Timer F runs at a much higher frequency than the Master timer, 10 times, roughly. This way, there are 10 equally spaces samples from my incoming signal that I can analyze for every period of the master timer. My incoming signal is of the same exact frequency as my outputs, just phase shifted by some degree. The ADC samples are put into an array by DMA, circular style. I'm creating a small array of 10 samples containing a reference sine, and cosine waveform. This is effectively my "window", which, for every 500 samples I collect (technically 1000, ping pong buffer style) I multiply my input waveform by the sine and cosine waveforms sample by sample, taking care to roll over every 10 samples for my sine and cosine tables. I th

I'm using an STM32H743VIT6 (rev V in LQFP100 package), powered at 3.3V and programmed with STM32CubeIDE.I'm using the ADC2 and ADC3, and also want to use the VREFBUF voltage (available on VREF+ pin) programmed for 2.5V. The *.ioc file is generated with:VREFBUF Mode -> internal voltage referenceInternal Voltage reference scale -> SCALE 0: around 2.5VUnfortunately I measure 3.3V on pin 20 (VREF+) instead of 2.5V!In the generated file stm32h7xx_hal_msp.c,  in the HAL_MspInit(void) function I see: /** Enable the VREF clock */  __HAL_RCC_VREF_CLK_ENABLE();   /** Configure the internal voltage reference buffer voltage scale */  HAL_SYSCFG_VREFBUF_VoltageScalingConfig(SYSCFG_VREFBUF_VOLTAGE_SCALE0);   /** Enable the Internal Voltage Reference buffer*/  HAL_SYSCFG_EnableVREFBUF();   /** Configure the internal voltage reference buffer high impedance mode*/  HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH

I'm designing a custom PCB using an STM32F103 microcontroller to control a triac-based light dimmer. The firing angle for the triac is determined by reading the voltage from the potentiometer.The potentiometer output is routed through a header and then directly to an analog input pin (PA0) of the STM32, which uses the built-in ADC to read the value. For power supply filtering, I'm using an LC network to separate the analog supply (VDDA) from the digital supply (VDD), with the usual decoupling capacitors.This project is part of my effort to learn how to build custom PCBs and improve my practical electronics design skills.My main question:Should I add an RC low-pass filter right at the analog input pin (PA0) for improved ADC readings?The potentiometer wires might be picking up noise.I want smooth, stable ADC readings to avoid flicker or erratic dimming.Does the STM32 ADC have any internal filtering/signal conditioning?If I should add an RC filter, what typical resistor and capacitor valu

I'm trying unsuccessfully to erase a 4K sector at 0x73ff0000 using STM32CubeIDE code, but the STM32CubeProgrammer works fine.  I've tried using BSP_OSPI_NOR_Erase_Block() and MX25LM51245G_BlockErase() with no luck. My code base is the HTTP_IOT_WebServer example.  My basic code is (where addr=0x73FF0000 and EFLASH_SECTOR_MASK=0x03FFF000)  ------------------------------------------- BSP_OSPI_NOR_DisableMemoryMappedMode(0);   rc = MX25LM51245G_BlockErase(&hospi_nor[0], MX25LM51245G_SPI_MODE, MX25LM51245G_STR_TRANSFER, HAL_OSPI_ADDRESS_32_BITS, addr & EFLASH_SECTOR_MASK, MX25LM51245G_ERASE_4K);   BSP_OSPI_NOR_DisableMemoryMappedMode(0);  ------------------------------------------- Any idea why this doesn't work? Is the Programmer doing anything I'm not doing?   -Marty

I wanted to do a full chip erase using STM32Programmer (I am trying to debug a custom bootloader) but kept getting the error "Mass erase operation failed.  Please verify flash protection".I sent the following option byte screenshot to ChatGPT....ChatGPT said... Problem: PCROP ProtectionIn your PCROP Protection section:PCROP1_STRT = 0xFFFFPCROP1_END = 0x0000PCROP_RDP is enabledThis is an invalid PCROP range: start at 0xFFFF, end at 0x0.That effectively protects a huge chunk of flash against erase/program.So even though WRP and RDP are fine, PCROP is blocking your erase.FixIn STM32CubeProgrammer → Option Bytes → PCROP:Set PCROP1_STRT = 0xFFSet PCROP1_END = 0xFFUncheck PCROP_RDP unless you specifically need PCROP linked to readout protection.Apply changes (Program Option Bytes → Reset).Retry Full Chip Erase with ST-Link.  I did the suggested fix but it obviously didnt work.But worse still, I cant even change the option bytes back to as they were because I get the

Hi,  I designed the us and ms delay functions using timer 2 and 4. Initially in the PLL source, I was using HSI, but it had some errors, so I switched it to HSE. I was using my delay function to control the DAC output, but when I switched to HSE, all my delay functions became twice as long.This is my code.while (1){/* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ HAL_DAC_SetValue(&hdac, DAC_CHANNEL_1, DAC_ALIGN_12B_R, 2854); // Delay_us(500);HAL_DAC_SetValue(&hdac, DAC_CHANNEL_1, DAC_ALIGN_12B_R, 868);Delay_us(500);HAL_DAC_SetValue(&hdac, DAC_CHANNEL_1, DAC_ALIGN_12B_R, 1861);Delay_ms(10);} This is the waveform of the oscilloscope.  In the clock tree settings, I only switched the clock source to HSE, and the divider settings did not change. I wonder why this happened. Best,  

Hello everyone, I'm using two STM32H503 boards.  One is programmed as an I3C controller, the other as an I3C target, and I'm trying to achieve the following sequence on the I3C bus: IBI from target -> Repeated Start -> Private Read  I find two things in RM0492 that may be helpful for my question: One is in Figure 418, there is the following note with 2 asterisks :Repeated start (Sr) if there is a pending transfer to execute and if I3C_DEVRi.SUSP = 0, else stop (P) in push-pull.The other is that there is a register called I3C device x characteristics register in RM0492. Here is the following description in RM0492, I set bit19 SUSP to 0, so that C-FIFO and TX-FIFO are not flushed after an IBI request.Based on this description, I preload a private read with C-FIFO before IBI, but I still saw that IBI completes with STOP, and then a START with private read. Is it possible to generate a repeated start after an IBI request? Does Hardware support for this sequen

Hello, I am struggling to use the following ST library for a project I am working on, I am using an stm32u5 with an MX25UM51245G NOR chip connected to the OSPI1 bus.  The library provided is setup to use XSPI_HandleTypeDef, Can this library be used when using the OSPI bus?ST MX25UM51245G Library on github Thank you

标准时间（标准时间)的标签产地和芯片产地不一样,请问这个是否正常 Translation: The label on this device (Standard Time Clock) indicates different countries of origin for the product and the chip. Is this normal? Edited by ST moderator. In next time please use English as this is an international community. 

I'm reading the RM0008 Reference manual.....I can't find a description of the registers and events associated with the entry point of Vector table for USB_HP_CAN_TX and USB_LP_CAN_RX0....What does it mean USB High Priority and USB Low Priority ?How do these relate to the events?I'm studying Table 63. Vector table for other STM32F10xxx devices...

Hello, I am working on STM32U5G7VJT6 with FDCAN1 peripheral.In CubeMX I configured 8 Extended Filters, and in my code I set them as dual filters. That gives me a total of 16 CAN IDs that can be allowed by hardware. Now my application requires filtering of around 50 unique Extended IDs. Since the hardware allows only 8 filters (dual = 16 IDs), I am not sure how to configure this efficiently for 50 IDs. My questions are Is there a way to extend the number of hardware filters beyond 8 (e.g., using extended, or any advanced setting)? If not, what is the recommended approach for applications needing more than 16 IDs? Should I: Use a broader mask in hardware filters (to accept a group of IDs), and then filter the exact IDs in software? Or is there another technique for optimizing FDCAN filters for larger ID sets? Any suggestions or example implementations would be really helpful. Thanks in advance!

I am using the DAC on the NUCLEO-L433RC-P board for development and have also designed a custom PCB using the STM32L433.The DAC is used for audio voice prompts (12 bit, 44.1kHz stored in external flash) and fed into an audio amplifier (TI LM48100Q).However, I am getting hiss and interference from a flashing LED on my custom PCB (but not so much on the NUCLEO-L433RC-P board).I decided to try using a bench PSU to power the VDDA and VSSA pins on the NUCLEO-L433RC-P board, in case the SMPS on my custom PCB was causing the hiss.Bbut I was suprised that the DAC still worked even though the VDDA and VSSA pins were floating after I modified the board.Why does the DAC work when the VDDA and VSSA pins are floating ?I measured the voltage on the VDDA pin (with reference to the VSSA pin) and it was around 1.6V.When I did connect the STM32 VDDA and VSSA pins to the bench PSU and supplied it with 3.3V, it made no difference to the behavior.Below are the modifications I made to th

I want to connect the STM32L433VCT6 to the ML22530TB (ROHM) using SAI communication.Where should I connect the ML22530TB's LRCLK, BCLK, SAI_IN, and SAI_OUT pins on the STM32L433VCT?

I am having the worst time trying to get ANY MCU on the planet to work right for this project. I want to build an i2s-USB bridge essentially. I can get the clocks right, I can get data from i2s (WM8782)➞DMA(Circular)➞|WALL|The only provided examples for any device that I have found that actually work have been DAC implementations. That's neat and all. But I want to make an acquisition of audio and stream it to my computer. I wish to make an Audio Interface.I have tried so hard, so many times, and failed so miserably every time.   A few times I have actually managed to rewrite the USB Descriptors well enough to get some remnants of wrecked audio stream to my computer, a sign of life at least. But when I had managed that, it was with a simpler device (STM32F411CEU6) and I hadn't gotten the clocks right, I was unaware at the time of the depth of complexity. I bought an STM32H723ZTG6, it checked all of the proverbial boxes. SAI, fast clocks, provided HSI48 just for USB, the

To which models does this document apply https://www.st.com/content/ccc/resource/training/technical/product_training/group0/0f/de/60/a5/80/9f/48/dc/STM32H7-Analog-OPAMP_OPAMP/files/STM32H7-Analog-OPAMP_OPAMP.pdf/_jcr_content/translations/en.STM32H7-Analog-OPAMP_OPAMP.pdf? Do any MCUs of the STM32H7R3/S3 series have the built-in opamps? Any information on this subject except this AN?

I want to connect the STM32L433VCT6 to the TLV320DAC3100 using SAI communication.Where should I connect the TLV320DAC3100's MCLK, BCLK, WCLK, and DIN pins on the STM32L433VCT?

Hello Team, Good Day ! Considering USB Specification , D+ line Pull-Up Should be high Once USB Connectors Plugs in , I Tried to Implement Following SCH to accomplish it. 3.3V Enabled through Transistor Q4 (MMBT2222ALT1G).  VBUS Signal Comes from Voltage Divider Network when USB Plugs in , See Below : J14 is USB 2.0 Type B Connector. Issue is When I plugged USB , Voltage Down to 2.5VDC from 2.8V @ L2 pin 4 ( i.e. D+ line). Ideally , It should be (3.3V- Vce ). As per USB specs. It should be Minimum 2.8V on D+ pull up.   Device is : STM32F303    Regards, Bhupendra

I am using an STM32H743 FMC to connect to the FPGA to do data transfer. (SRAM type with 16-bit data. I tried this on an STM32F429 and the test was successful)  The test is to send some amount of data to the FPGA through FMC.The code is quite simple. Write some data to 0x6000 0000 and check if the FPGA can get the data correctly.My discovery is that if only a small amount of data has been sent and  chip select signal FMC_NE1 will remain high and no waveform can be observed...Send 100 data and FMC_NE1 remains high If I send lots of data(for example, 10000 data) then FPGA can receive data correctly, but the data FPGA receives starts from 2020(this number is also random, some time 1820 some time 3020, etc)This phenomenon does not happen on F429... If I send 10 data and the FPGA can receive 10 data correctly... 

After migration to STMCubeIDE v1.19.0 and STMCubeMX v6.15.0 the working project based on STM32H7 Nucleo-144 Board (STM32H723ZGTx) shows red x for Pinout & Configuration caused by LWIP -> Key Options -> Network Interfaces Options with red x. This error blocks the code generation process.Any suggestions?Thanks.JYI

I am trying to send data from STM32 to the FPGA by using FSMC. My goal is to send data as fast as possible so I set FMC clock to be maximum speed and set sram clock cycles to be as low as possibe. I use FPGA internal Logic Analyzer to capture data from FSMC and the result is shown as below. I found that the data was sent one by one instead of burst mode(send data continuously) and the speed was well below requirement... I want to know how to use burst mode in FSMC?(Since I am using an FPGA to receive data so any mode is ok(PSRAM, SRAM, SDRAM, nano flash, etc)) 

Hi,I have a new design using the STM32H725IGT. The STM32H725IGT is a 176 pin QFP. The power rails have all checked out as good but I can't connect to it to program it. I have tried two ST-link V2's and two separate boards with no success. Both ST links updated their firmware successfully  and are seen by the CubeMX IDE. We are also using the Olimex adapter to enable a smaller connecter. This is the PCB layout of that:The on-board connector is the Samtec FTSH-105-01-F-DV-007-K, so an Olimex ARM-JTAG-20-10 is used to convert the large 20-pin ST-link connector down to 10 pin. As can be seen in the above image, SWCLK goes to pin 138 of the STM32H725IGTSWDIO goes to pin132 of the STM32H725IGTOn the FTSH-105-01-F-DV-007-K, pins 3 & 5 are GND, 1 is +3.3V, 2 is SWDIO, 4 is SWCLK. Pin 6 is connected as JTDO-SWO. Pins 6 and 8 are, I believe not used by the ST-link. Pin 10 connects to pin 33 of the STM32H725IGT, nRST. The nRST is labelled JnTRST for JTAG programmers, but it is