STM32 MCUs Products

Hi, I'm trying to do an external loader according ST's MOOC and this forum https://community.st.com/t5/stm32-mcus-products/stm32h5-external-loader/td-p/601134.My code pass on all ST's tests of memory, but when I generate a stldr it does not read on cubeprog.I attached my project and log of cubeprog.I already do the same with a G474 without problems. BR

Hi, On STM32G071CBU6, when PB15 is used as CC2 with DBCC2 shorted to CC2, does the ROM bootloader ever drive PB15 as SPI2_MOSI, or does the CC/dead-battery own the CC2 pin and that path always takes priority? This detail is critical for our design because the device is bus-powered and relies on the dead-battery path to manage initial power-up. If the bootloader were to override PB15 and drive it as SPI2_MOSI while the flash is blank, it could cause a power drop when the ROM bootloader starts. I checked the datasheet, reference manual, programming manual, and bootloader manual, and none of them explicitly state how the ROM bootloader handles SPI2_MOSI when that pad is also CC2 with DBCC shorted. Could you please clarify? Thanks

Hi. I'm trying to read data from w25q64. When i erase and write the chip and then read it, i receive true data.But when i only read data, my chip is blank and i receive 0xFF.

Hi, I'm using a Nucleo-F446RE Board and I'm trying to set up a basic DAC with DMA configuration without HAL-libaries.The configuration without DMA works just fine, I can measure correct voltages with my oscilloscope on PA4 as intended. My following DMA configuration sets the PA4 always on 0V, nothing happens.I checked the debugger and all registers are being properly set, DMA and DAC both have their clock and values.It just doesn't copy the values into DAC->DHR12R1. I also checked the Flags in DMA_LISR, but no error there.I'm probably missing somehow on how to start the whole process, so my last iteration of code tried to mess with software triggers. I also tried all combinations of PSIZE and MSIZE, as well as uint8_t and uint32_t arrays instead of uint16_t. I feel like I followed the stream configuration procedure from the reference manual, but I probably missed some small, gritty detail.Anybody got code for a similar MC

Hi. I'm trying to read data from W25Q64 flash memory.These are my connections:And these are my SPI and RCC and GPIO settings:

Hello ST experts,I have a weird experience with UART communication between two STM32G4 microcontrollers. MCU1 sends 10 bytes to MCU2 via UART. Both UARTS are configured with 9600 Baud rate with DMA in circular mode. The Problem arises when the MCU1 is turned on, it sends 11 bytes which the first byte is 0x00 in case I need only 10 bytes to be received. Can you help me in this issue?Best,Davood.

Hello,I am using the VENC_RTSP_Server example located in:STM32Cube\Repository\STM32Cube_FW_N6_V1.2.0\Projects\STM32N6570-DK\Applications\VENCThis example shows how to use the VENC block and stream H.264 video through RTP/RTSP using Ethernet.I want to send the encoded H.264 video stream to another controller through SPI instead of RTP/RTSP.My questions are:1. What is the input data format of the H.264 encoder (VENC)?Is it receiving YUV420/NV12 from DCMIPP, or some other format?2. Is there an API in the VENC example that allows access to the encoded H.264 bitstream buffer(pointer + size), before it is sent through the RTSP server?3. Is there any example or documentation that shows how to use the H.264 encoder output without RTP/RTSP?For example:Camera → DCMIPP → VENC(H264) → SPII only need to sending the encoded H.264 data through SPI to another controller.Thank you!

Hi, everyoneI recently encountered a strange phenomenon. I opened three DMA channels on the STM32G474RBT6.The first one is Channel 1 of DMA1 (circular mode), which is used for automatically collecting the data converted by ADC.The second one is channel 8 of DMA2 (normal mode), which is used to transfer the calculated data to the timer for updating the PWM.The third one is Channel 1 of DMA2, which (normal mode) is used to send serial port data of variable length. The first two did not enable the interrupt service function.But if the DMA in the third case does not enable the interrupt, the serial port sending process will be stuck (the HAL library shows that the DMA2channel1 is in the “BUSY" state). If the interrupt is enabled, this situation will not occur.However, the interrupt service of the first two I didn't enable DMA can still run normally. The data of the ADC can be automatically transmitted, and the timer can also send out the correct

In my embedded software project, I need to write a bootloader. I wrote an application code for the bootloader and testing, and everything is fine so far, but the delay function in the application code is not working. I think the reason for this is the Vector Table. I wrote the vector table to the RAM address, but it didn't work at all. It jumps to the application code, turns on the LED, but does not toggle. I would really appreciate your help. (STM32f030c8t6 board)#define APP_START_ADDRESS 0x08006000 // User application start address #define APP_START_ADDR 0x08006000 #define SRAM_BASE_u 0x20000000 #define VECT_TABLE_SIZE 0xC0 // 48 vectors * 4 bytes void JumpToApplication(void) { // 1. Dsiable all interrupts __disable_irq(); // 2. Deinit HAL and RCC (optional if bootloader did init) HAL_DeInit(); HAL_RCC_DeInit(); // 3. Copy vector table memcpy((void*)SRAM_BASE_u, (void*)APP_START_ADDR, VECT_TABLE_SIZE); // 4. Remap SRAM

I am designing a system that will utilize the dual bank feature of the STM32 devices to make a robust system for OTA updates. I am currently using a STM32U545 for my project and have questions about writing to the FLASH_OPTR to change the SWAP_BANK bit.My setup has an external microcontroller connected to my STM32U545 that interfaces through UART and has control of the BOOT0 pin and the RST pin of the STM32 device. I was confused by the statement in the AN3155 pg. 20 when it talked about the Write Memory command and said "If the Write Memory command is issued to the option byte area, all bytes are erased before writing the new values, and at the end of the command the bootloader generates a systemreset to take into account the new configuration of the option bytes". What does it mean by all bytes are erased? My current plan was to use the read memory command and read the register FLASH_OPTR at 0x4002 2040 and then read bi

Hello, We are facing an intermittent CAN-FD issue in the field and would appreciate guidance from the community. Our system has two devices on the bus (no other device on the bus) using a request–response architecture. The master sends a request every 30 ms and the slave responds. This setup is deployed in hundreds of units running continuously (24 hours). Out of these, around 3 to 5 units per day show acknowledgement errors, which we track through the CAN protocol error counters. The behaviour is unusual: • The issue appears randomly on any unit.• No bus-off condition is ever reported.• Despite no bus-off, communication between the two nodes temporarily stops.• Communication recovers automatically after a few seconds without any intervention. Initially, we suspected a physical wiring problem. We re-checked all connectors and even secured them with glue. The bus has 120-ohm termination at both end

Hello,I have not found the maximum TRACECLK frequency of the STM32H725 in the documentation. It looks like it is generated by PLL1 with flexible division ratios and thus can attain values that are not realistic for I/Os (100 to 220 MHz for Speed 11 and 2.7 V ≤ VDD ≤ 3.6 V as per p.165 of DS13311).Is the maximum TRACECLK set by the maximum I/O output frequency or is it restricted to another value? Regards,Bernd

I am having a custom board having STM32N657I0H3Q interfaced with quad flash MX25R6435FM2IL0. I am unable to access (both read and write) to the flash MX25R6435FM2IL0.I have attached Saleae capture (configured the flash in single mode only for Saleae capture). Also, debug log of EMM running in FSBL.The eval board (DK board) is having MX66UW1G45G doing good. The logs looks like EMM could not access the SFDP structure.  

Hello, I am reading 6.3.30 LCD-TFT controller (LTDC) section to interface with DS90C385A (LCD) or ADV7125 (VGA) Assume that LCD Clock (pixel clock) polarity is set to high. Ideally, we can expect rising edge of clock aligned to the middle of the data.  But I can see there is a more time for setup and less time for hold. Refer the figure 46 of datasheet.      Note: I am going configure pixel clock low for DS90C385A (LCD) and high for ADV7125 (VGA).  Also, I need to ensure HW work till 150MHz clock.       

Hello, How to perform dual-core communication on STM32H747?

There is this errata for STM32G0B12.2.10 Prefetch failure when branching across flash memory banksDescriptionIn rare cases, the code prefetch may fail upon branching and function calls across flash memory banks,regardless of the DUAL_BANK and nSWAP_BANK option byte settings. The failing prefetch then provides anincorrect data to the CPU, which causes code execution corruption and may lead to HardFault interrupt.The workaround is obvious, either disable prefetch when jumping to code in the other bank and enable it again afterwards or use a small "trampoline" function in RAM. We can live with that, as our software is split into separately compiled "core" and "application" parts loaded into separate banks, having only a handful of interface functions there would be e.g. no jumps into library functions in the other bank. What about exceptions and interrupts, how are they affected? The ARM

I have seen that it takes about 28 ticks to read registers, so I think my stm32h750 runs really at 17Mhz, it seems is not risk, so perhaps it exists another more fast stm32 micro that have more 17 MIPS 

This is a pretty basic question but I would like a bit of clarity if possible.If a GPIO pin is configured for the fsbl code can it also be used in the Appli code?If so how would you go about defining it in the Appli code? There doesn't seem to be an option to use a GPIO pin in both fsbl and Appli in STM32CubeMX or do you have to configure it manually in the Appli code?

Our company has a chip that outputs data via DCMI, though it does not employ a standard DCMI interface. It lacks a horizontal synchronisation signal, possessing only a vertical synchronisation signal. Could you advise which chips are capable of receiving such data? If available, please provide specific chip models and concrete code examples.   Edited by ST moderator: This post has been translated from Chinese to comply with the ST Community guidelines.

Hello Expert, Could you please provide guidance on the issue below?  We are using the following setup:- MCU: STM32G0B1CCTx- Software: X-CUBE-TCPP 4.2.0 with USBPD Application 4.2.0 Dual Role- Board Part: TCPP0203 v1.2.3 We are developing a USB PD board.When we plug in an Android smartphone (USB Type-C port), the phone does not detect the connection.Attached is the log showing three plug-in/plug-out attempts.(we plug in and out 3 times)From the log, it appears that after attachment, the connection detaches immediately, then the roles switch, followed by another detachment.We have already tried increasing the CAD source/sink toggle time from 100 ms to 144 ms, but the issue persists.Could you advise on possible causes or solutions? Thanks. DEBUG 86569 0 -- BSP_USBPD_PWR_SetRole : SNK -- 96DEBUG 86609 0 -- BSP_USBPD_PWR_SetRole : SRC -- 97D

Using Nucleo-U545RE-Q, SPI2 Full-duplex Master, default GPIO selected by STM32CubeMX v6.15.0 with LL selected for implementation.Config clock for max 160 MHz and prescale SPI by 8 for 20 Mbps. Add GPDMA Ch2/3 for SPI2 TX/RX.I double checked the output configuration code generated by the CubeMX against the Cube_FW_H5_V1.5.0 Examples_LL: SPI_TwoBoards_FullDuplex_DMA_Master_Init, and it matches exactly but for peripheral selection. Jumper-wire PC1-to-PC2 (CN7.36-to-CN7.35) for simple SPI loop-back test. With this configuration, the loop-back works when I implemented the SPI full-duplex transfer by LL blocking code. But trying to use the GPDMA channels results in no data, no DMA IRQ for TC or DTE, no SPI IRQ for anything. Below is the simple code to try to get a transfer going, there is initialization code that enables all SPI and DMA interrupt sources and handles the IRQ by clearing the flag and setting the local global booleans that you see belo

Hi,I have a custom board with an STM32L031C6 and I'm trying to read the internal temperature. The board is battery powered at about 2.6V and the vdda is the same.If I read the ADC channel with vrefint, it returns a value of about 850, which, when passed to the function __LL_ADC_CALC_VREFANALOG_VOLTAGE(adcVal[4], LL_ADC_RESOLUTION_12B), returns a calculated VDDA of 6V, which is obviously incorrect.Using this vref to calculate the internal temperature obviously results in a value that's out of range.The same thing works correctly on a NUCLEO-C031.What am I doing wrong?Thanks!

Hello,I configured TIM1 as shown in the attached image: Everything works as expected I am controlling an inductive load which oscillates heavily after the PWM is turned off. I therefore decided to immediately short the low-side MOSFET (CH1N) to ground if a BREAK or

Hello ST Support Team,I'm working with the STM32L031K6U6 (32-pin UFQFPN package) and need clarification on ADC channel mapping.Question: Is there an ADC Channel 9 available on the STM32L031K6U6, and if so, which physical pin does it map to?Context:- I'm trying to use PB1 as an ADC input- Documentation suggests ADC Channel 9 should be availableCould you please confirm:1. Which pins have ADC capability on STM32L031K6U6 32-pin package?2. Is ADC Channel 9 available on this specific package variant?3. If ADC Channel 9 exists, which physical pin does it connect to?Hardware: STM32L031K6U6 (32-pin UFQFPN package)IDE: STM32CubeIDEHAL Version: LatestThank you for your assistance.

Hello, I expect this to be flagged before but couldnt find during search. Is Table 116 for the stm32f43xx on page 768 missing registers for CRYP_K2LR / CRYP_K2RR at offset 0x30? TIA