STM32 MCUs Products

Hi developers,   I'm new to STM32 MCU, but recently need to use it for a automotive Ethernet board design. The ethernet PHY I am going to use supports the jumbo frame up to 16kByte. Do anyone happen to know if STM32F407VGT6 can also support this jumbo frame feature or only for standard 1518Byte eth frame?   (if not, ss there any MCU from ST suggestion that support this jumbo frame feature.    Thanks!!!

I'm trying to read and write SPI bytes from an STM32F446RE chip with DMA.  The STM32f4 is the slave and a RPi is the master.  The first SPI read works fine (data read into buffer starting at index 0), but subsequent reads have the data starting at index 1 instead of index 0.  I tried resetting the SPI peripheral with this bit of code I found on the forums: #define RESETSPI {\ HAL_SPI_Abort(&hspi2);\ __HAL_RCC_SPI2_FORCE_RESET();\ __HAL_RCC_SPI2_RELEASE_RESET();\ }  This fixes the reading off by 1, but it results in the last byte sent back to the PI to be wrong. Does anyone know what might be happening or how I might address it?

Hello everyone,I just started using stm32cubeide. I'm trying to do I2S protocol.I'm trying to filter using the MP45DT02 microphone on my card and get noise-free sound as it is to the speaker on the MAX98357A Amplifier card. When I checked my connections and everything, I could not detect the error. Attached is the video I watched and applied at least 8 times without error. I also share my codes in the attachment.Can you check my codes, is there anything missing?Best regards...-MelihCanhttps://youtu.be/JuXKeyFraF4 /* USER CODE BEGIN Header *//********************************************************************************* @file : main.c* @brief : Main program body******************************************************************************* @attention** <h2><center&gt

Hi!I use the RTC of a STM32G030K6T. It is clocked by LSI (appr. 32kHz). And PREDIV_A is 0x0 and PREDIV_S is 0x7FFF. So I expect that RTC_SSR overflows every 1.024sec...But: It overflows every 0.687sec... As if the LSI frequency would be 47712Hz...I mentioned this after I soldered the positive contact of a LiFePO4 battery... Now I cannot easily disconnect power... Triggering the reset pin does not change the fast RTC... A software reset does not help, too...How could I possibly damage the LSI by making a solder joint at the other side of the board? I even have a voltage clamp at 3.5V and a LDO (3.0V) between that solder joint and the STM32G030.Or is it more likely that I made some last minute firmware changes? What could that be?Thx.Bye.

Hi I m using SPI DMA on H7 series, and notice under SPIx_TX and SPIx_RX there are at least 14 DMA channels to choose from, i.e DMA1 Stream 0-7 and DMA2 0-7. Can i select these "channel"  randomly or is there a reference manual that state otherwise? Likewise i saw the same case in USART DMA too, anyone can advise?

I want to know the reliability data for M41T0M6F.so please provide to me soon. thank you

Is STM32F446MEY6MTR of MIL grade microcontroller? Is any variant of STM32F446xx have MIL 464/461 or MIL810G standard?

Hey everyone, I'm learning about USB CDC and soon USB HID. I think I successfully program the stm32 as a cdc device because I can connect to it, and I can read and write serial commands through a terminal. I can even catch the serial buffer through the CDC Receive function. I used cubemx and middleware for generating the usb cdc But my question is, on device manager, the stm32 cdc does not show up as "stm32 virtual comport" but as a regular Usb serial device. This happens to in windows 10 and 11. Also the PID and VID numbers are different from the usbd_desc.c. any help would be greatly appreciate it. im not sure if this is needed, but this is what I have for cdc control fsstatic int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length

I used STM32H563 transmit a message through I3C CCC direct.I create a new CCC command "0xA0".Control send the command to target.But target will enter HAL_I3C_ER_IRQHandlerUesd the general command "0x89".The target can receive this command. The Buffer is same. 

Does anybody have an example code how to use SAI in STM32U5A5 as PDM interface?I use STM32U5A5, with LQFP64 package. So, I understand from datasheet: the SAI (I have just SAI1 available om pins), supports PDM interface (for MEMS MICs). My package has just the pins for SAI1_D1, SAI1_CK1 and SAI1_CK2. OK.And I saw, that the _B part for SAI does not support PDM - OK. All "four pairs" of SAI PDM is not possible with my package - OK.Question:Is it important to "group" the signals, e.g. SAI1_D1 with SAI1_CK1 (channel 1 signals)?Or: is it possible to use SAI1_CK2 (which is SAI1_SCK_A on my board), configure it as PDM CLK (bus as channel 2), but use SAI1_D1 (which is SAI1_SD_A) for the PDM MIC data?I mean: would be _CK2 synchronous to _CK1, so that I can use _CK2 but together with _D1?

Hi,everyone! I want to know if FDCAN ( I'm using STM32H7) has lost the automatic Bus-off Recovery mechanism. Looking Forward to get your reply.Thanks!

I have an STM32WB55CGU6 on a custom board with a 32MHz HSE. I'm using low power uart1 with PA2 & PA3 pins. My settings for it are: - baud rate 9600- word length 8 bits- 1  stop bit- parity noneIt won't transmit. Cube doesn't receive it, any terminal doesn't receive it and the pins just remain low all the time. When I tried adding an if clause to test if the result is HAL_OK, the code wouldn't even upload. What's up here, shouldn't be this hard getting basic UART to work.code: uint8_t text[]={0,1,2,3,4,5,6,7,8,9}; /* USER CODE END 2 */

I tried to set up a UART connection from my custom board to my PC but encountered some problems and after a bit of probing, it seems that UART TX and UART RX are connected to GND. Do I need to enable UART somewhere for the ST-LINK ? Also why do some drawings display pins 6 and 4 as GND but some of them display them as UART pins?  

I'm trying to send a fixed length packet in SPI slave mode from the STM32 via DMA. The SPI master may send/recv longer than that fixed length packet. It would be nice if the STM32 just sends 0 one the transactions is complete, but it seems to want to send 0x02 or 0x80. I'm wondering where this is coming from and if there are any ways to get it to send 0. init_struct_.txDmaChannel->CCR &= ~DMA_CCR_EN; init_struct_.txDmaChannel->CNDTR = descriptor.length; init_struct_.txDmaChannel->CMAR = (uint32_t)descriptor.txBuffer; init_struct_.txDmaChannel->CCR |= DMA_CCR_EN;dma configuration init_struct_.txDmaChannel->CPAR = (uint32_t)&init_struct_.spi->DR; init_struct_.txDmaChannel->CNDTR = 0; init_struct_.txDmaChannel->CCR = DMA_CCR_DIR | DMA_CCR_MINC; init_struct_.txDmaMuxChannel->CCR = init_struct_.txDmaMuxId;

The application note AN2834  (https://www.st.com/content/ccc/resource/technical/document/application_note/group0/3f/4c/a4/82/bd/63/4e/92/CD00211314/files/CD00211314.pdf/jcr:content/translations/en.CD00211314.pdf  page 36)  mentions a "SAR ADC sampling estimation tool" that is "available upon request". I am new to the ST developer community and was wondering how can I request and obtain this tool? Thank you in advance,--Stefanos

In the FD_CAN register, there is a CEL[7:0]:, REC[6:0]: and TEC[7:0]:,The CEL register is not being reset on read and goes into the Bus-Off mode.Do I need to also reset the REC and TEC register?I am currently using the HAL_GetErrorCounter() function to read the register. 

JW

I am a bit confused by the documentation on oversampling and the required trigger rate.  I'd like to do 2 conversions a second on 5 channels using 256x oversampling.  I have the ADC in continuous mode. I am triggering off TIM3 update.  It's not clear to me if I trigger once every half second to get all 256 conversions on all 5 channels or if I have to trigger 256 times each half second.  If there is only one trigger, does the first channel get sampled 256 times and then the second 256 time until the fifth channel? Thanks. 

Hi Community,I am using the controller , STM32L072CZT6. I am currently working on Fota functionality .I am downloading a binary file from ftp server and I need a crc verfication for the downloaded data. I am using the default CRC settings in the .ioc file.The polynoimial is 0x04c11db7Init value is defaultI couldn't find a tool that could generate the crc with this polynomial. Please let me know if there is any tool available like JFlash (which uses a diffrent polynomial 0xebd88320). I am currently trying to generate the crc for using it with Jflash:The document states that:a. Everything that is not covered by the data file (gaps in the data file, unused sectorsetc.) which is opened, is assumed as 0xFF during the CRC calculation. (Is this the init value ?)b. The polynomial which is used for the CRC calculation is 0xEDB88320.These are the .ioc configurations wrt Jflash Please let me know if the init value provided is correct or no

Hi to everybody.I'm using H5 and FREE RTOS. I'm porting a project from M3 , than M4 now to H5. I used LL for all the periferals, but moving to HAL isn't a probelm (... but I prefer  LL!).On M3 and M4 I used a timers to "serve" the RTOS scheduler, then SysTick for a simple delay (yes, also on a task!). E.G. when I need few milliseconds between toggling a output while driving the display.With H5 I can't use something like "LL_mDelay(100);" because it stuck.How I can enable systick with H5 (voa MSX CUBE) the LL_mDelay (or HAL_Delay) to measure a time, or simply get a systick?Thanks in advance. 

What is right? 7 or 8 bits?

JW

Hello community! I am developing an app that is running in an H7 MCU, the M7 core app is "turning on" the M4 and then is running to an external flash where is the actual M7 code.I am looking to implement an update in this M7 "bootloader". As i understand, before "turning on" the M4, i can interact with the flash region where the M4 has its code to run, so my idea is in the M7 bootloader to start an USB port to detect an USB disk and if there is a .bin file for each core, to write the M7 in the external ram (using a code similar to the developed external loader for example?) and for the M4, just a write in the M4 memory location? I look forward for your commends dear community :) Thanks!

Hello, I'm studing I2C on stm32g071rb and I have a question about it.In the datasheet there is this line: "In the case of a write transfer, the TXIS flag is set after each byte transmission, after the 9th SCL pulse when an ACK is received", but for the last byte TXIS remain LOW and TC become HIGH.It's correct that for the last byte that I have to send via I2C, the TXIS bit remain LOW?For example if I have to send(master to slave): 0x00, 0x01, 0x02I set the CR2_NBYTES bit (3 << I2C_CR2_NBYTES_Pos)...etcBut after send the 0x02 byte, only TC is HIGH...so also the TXIS bit should be HIGH in this case?Thanks Simeon

Hello,I'm using ADC together with DMA.At first start of ADC and DMA all worked like expected.At 2nd and following starts, the first value received from DMA is always zero / invalid.Now I have found out that it works if between two DMA transfers I useLL_ADC_Disable(ADC2);and afterwardsLL_ADC_Enable(ADC2);//code snippet:LL_DMA_SetDataLength(DMA2, LL_DMA_CHANNEL_1, 100U);LL_DMA_EnableChannel(DMA2, LL_DMA_CHANNEL_1);LL_ADC_REG_StartConversion(ADC2);while (LL_DMA_GetDataLength(DMA2, LL_DMA_CHANNEL_1) > 0U){}LL_ADC_REG_StopConversion(ADC2);LL_DMA_DisableChannel(DMA2, LL_DMA_CHANNEL_1);LL_ADC_Disable(ADC2);while(LL_ADC_IsDisableOngoing(ADC2)){}LL_ADC_Enable(ADC2); Now my questions:Is disable/enable of the ADC absolutely necessary?