STM32 MCUs Products

请问有人能提供一下STM32G030xx或者STM32其他系列MCU作为IIC从机进行通信的例程吗，谢谢。

Hello everyone, so it is my first time designing a board with stm32l476rg MCU. I was using the reference design from this sheet: https://www.st.com/resource/en/application_note/an4555-getting-started-with-stm32l4-series-and-stm32l4-series-hardware-development-stmicroelectronics.pdfWhen I was looking at datasheets to choose LSE and HSE I saw this note on section 7.7 of https://www.st.com/resource/en/user_manual/um1724-stm32-nucleo64-boards-mb1136-stmicroelectronics.pdf

Hi, I'm using the STM32H7 family and have spent several days trying to get dual mode working correctly with the STM32H723.  I finally switched to the STM32H753 so I could try the ADC_DualModeInterleaved example from the repository at STM32CubeH7/Projects/NUCLEO-H743ZI/Examples/ADC/ADC_DualModeInterleaved at master · STMicroelectronics/STM32CubeH7 · GitHub.  It seems to work, but I need regular simultaneous mode instead.In the code, I replaced the MultiModeInit.Mode =ADC_DUALMODE_INTERL statement with  MultiModeInit.Mode = ADC_DUALMODE_REGSIMULT, and also reconfigured the ADC channels as follows: //Original #define ADCx_CHANNELa ADC_CHANNEL_18#define ADCx_CHANNELa ADC_CHANNEL_19 //New//Original #define ADCx_CHANNELa_GPIO_PORT GPIOA//Ori

Hi,we are using ADC with DMA for internal ADC channel like internal Temperature sensor, VBAT, VREF but we are facing issue related to accuracy please help me on this Configuration:ADC channel:   adc_channel_config_t ADC3_temp_config = {        .channel       = ADC_CHANNEL_TEMPSENSOR,        .rank          = ADC_REGULAR_RANK_8,        .sampling_time = ADC_SAMPLETIME_810CYCLES_5,    };   adc_channel_config_t ADC3_vbat_config = {        .channel       =

Hello I am triyng to use STM32H735 with ethernet (ln8710A is the PHY) We have hardware fault when we connect the cable (se the itm print below)We use CubeMx version Version: 1.18.0ETH is in RMII conection is OK    

HiChip：stm32h723Peripheral:FMCConfiguration:FMC_NORSRAM_DEVICE , FMC_NORSRAM_EXTENDED_DEVICE;FMC_ACCESS_MODE_AFMC_ASYNCRONOUS_WAIT_ENABLEIf the extended device(eg. FPGA) do not assert NWAIT，the program on stm32h723 will crash. I want to know which register can set the timeout for the NWAIT signal to prevent a crash? Best regards,Andy Zhou

Hello,STM32F411 microcontroller.Where can I find what mode (input/output or pull-up/pull-down) to configure the GPIO for alternate functions? For example, for UART or SPI and so on.For example, for STM32F103 microcontroller, there are tables that help you select the appropriate GPIO settings for alternate functions (UART or SPI and so on) in the Reference manual. For STM32F411 microcontroller, there are not tables that help you select the appropriate GPIO settings for alternate functions (UART or SPI and so on) in the RM0383 Reference manual. There are this information (see figure bellow) in the RM0383 Reference manual, but there are no such clear tables as for the STM32F103 microcontroller.

Hello Using a STM32U5G9NJHxQ.Using a 646x480 1byte per pixel monochrome Dcmi camera --> 310080 bytes --> 77520 words (32 bits) --> according to AN5020 6.4.8 this means Double buffer mode for medium resolutions, continuous capture in my case.Based on DCMI_ContinousCap_EmbeddedSynchMode example, I made some changes to try the linked list and double buffer.Please see txt file attached explaining my testing.Please, is there any official example from Stm on how to configure stm32u5g9 Dcmi with linked list and double buffer ? Regards.            

Good morning, I am trying to debug an STM32H573II with ETM, but I cannot get it to enter that mode.Debugging without trace with SWD works correctly. I have used this environment: - uVision 5.42- ARM Compiler 6.21- STM32CubeMx 6.14.1 I have performed the following checks: - MCU Non_Secure mode. Avoid conflicts.- Enter debug mode with SWD.- Verified pinout.- Checked that JTrace - CortexM works ETM with other MCUs (STM32H7, STM32F4, tested)- Generate an empty project with STM32CubeMx, just to enter debug mode with trace  The JTrace log indicates a problem with the reset, but there is no problem if I debug with SWD and SWD+SWO. Can you help me, please?Has anyone had problems with any H5?  

Hello, so I was originally using printf with uart3, and that seemed to work fine. The characters were being printed as expected on a PuTTY terminal that I was using. I was using the following code:/* USER CODE BEGIN PV */ UART_HandleTypeDef *uartHandlerDebug = &huart3; // UART bank used for communication with computer for debugging /* USER CODE END PV */ int main(void) { /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); /* USER CODE BEGIN SysInit */ setvbuf(stdout, NULL, _IONBF, 0); //! Disables buffering for stdout HAL_Delay(1000); // Allow previous code to be erased /* USER CODE END SysInit */ /* Initialize all configured peripherals *

Setup: NUCLEO-H503RB with X-NUCLEO-IKS4A1, using STM32CubeIDE. To familiarize myself with I3C, I am playing around in this setup and have some source code which causes I3C interaction between the controller (Nucleo board) and two targets (daughter board). I have a logic analyzer attached. What I cannot get to work is the "direct RSTACT", i.e. configuring one of the two targets to reset itself. After everything has come up, I expect the targets' default reset action to be "1", i.e. I3C peripheral reset. After successful dynamic address assignment to both targets, I send a direct RSTACT (CCC 0x9A) to one target, configuring the reset action to be "0" (no reset), followed by the reset pattern. I would expect the other target to lose its dynamically assigned address and respond to a subsequent ENTDAA. But no one responds. Note that in my screenshots, the decoder is set to I2C rather than I3C (not supported) but

Hello,I have a STM32H75x design and suffer from read errors in DDR timing, no matter if run at 50MHz or slower.It seems that the data hold time of 1ns the H7 is violated. The data output hold time of the SPI NOR MX25L12845 flash is 1ns, which seems to be too short for H7. Due to the fact, that the clock edge takes also ca. 0.5-1ns, the timing should be safe in my opinion. Nevertheless, a read failure arises if the drive strength of the flash is lower than 45Ohm and GPIO pin speed is higher than MEDIUM.The H7 evaluation boards are equipped with Micron flash with 1.5ns and it seems that this value is fine for H7.Therefore I doubt the data input hold time of 1ns@3.3V in table 181:

Hi,I am currently using the following microcontroller (STM32F100C8T6B) in my design. I am using the STM32CubeIDE and I trying to build the project, but I am getting the following compiler errors from the "core_cm3.c" fileError: registers may not be the same -- strexb r3,r2,[r3]' Error: registers may not be the same -- strexh r3,r2,[r3]'Any help would be greatly appreciatedThanks,WJ This is the version for core_cm2.c/**************************************************************************//*** @file core_cm3.c* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File* @version V1.30* @date 30. October 2009** @note* Copyright (C) 2009 ARM Limited. All rights reserved

Hello Experts,I'm using the STM32L476 in one of my projects, with the main system powered at 3.3V (VDD), and a 1.55V coin cell (Murata SR621SW) connected to VBAT for RTC backup.The tamper pin (PC13) is connected to a normally closed (NC) anti-tamper switch, which means the circuit is only open when the enclosure is physically closed. I've configured the tamper detection in level detection mode with the following settings: Sampling frequency: 1 Hz Precharge duration: 8 cycles External capacitor: 1.8 nF Trigger on: Low levelMy concern is about the behavior of the RTC and tamper detection circuitry during a power-down event — for instance, due to a brownout or complete power loss. I’ve set the Brown-Out Reset (BOR) level to Level 4.In such a scenario, when VDD drops and the RTC switches ov

I've been getting some weird hard faults on an STM32U073RCT, which I've tracked down to the following conditions- In stop mode, waiting on an interrupt.- Debugging, with debug in stop mode enabled.- Interrupts are disabled.- An RTC interrupt occurs.When this happens, I get a hard fault a few instructions after the WFI - the exact distance seems to vary based on the instruction's offset. Single stepping though them does not cause a fault.I've attached a minimal cube ide demo project to replicate the issue. It requires a board with a crystal to run the RTC.Set two breakpoints, one at stm32u0xx_it.c:85 (for hard faults), one at main.c:126 (on success). Only the hard fault gets hit. Examining the stack shows the previous program counter was 0x8000248, which points to one of the NOPs.

Do I understand the datasheet correctly when I believe the internal 2.1v reference is something internal, and the AD is still operating within VCC/3.3v as upper limit? Copilot suggested this:  // Enable ADC1 and configure itRCC->APB2ENR |= RCC_APB2ENR_ADC1EN; // Enable ADC1 clockADC1->CR2 |= ADC_CR2_ADON; // Turn on ADC1// Configure ADC1 to use the internal reference voltage (1.2V)ADC1->CR2 |= ADC_CR2_TSVREFE; // Enable internal reference voltageADC1->SMPR2 |= ADC_SMPR2_SMP0; // Set sam

Hi,I am experiencing a packet loss issue using Peripheral-to-Peripheral DMA between UARTs.While Peripheral-to-Peripheral configuration is referenced in the STM32U585's Reference Manual, it is not available in the HAL library. Therefore, the DMA is configured for Peripheral-to-Memory mode, with the destination address set to the UART's Transmit Data Register (TDR). FIFO mode is not used.The reference setup I am using is based on the B-U585I-IOT02A, where no packet loss occurs.(MSI Clock)USART2_RX → USART3_TXUSART3_RX → USART2_TXThe packet loss issue occurs on another STM32U5 (u585cit6q) with the same software but different UART configurations. (HSE Clock)USART3_RX to UART4_TXUART4_RX to USART3_TXUSART3 is configured to use the RS485 protocol.

Hello, I use an external flash in memory mapping mode and I have a strange problem. The application is executed from the internal RAM, while the checksum is calculated on the data from the external flash (simple summing of successive bytes in a loop). Interestingly, sometimes I get an incorrect result, i.e. the sum is a bit smaller, e.g. instead of 3233257 it is 3233225 as if one byte had not been counted. Interestingly, later the program jumps to the application that is executed from the external flash and it works normally (does not crash). I tried to turn off D-Cache but it does not help. Since the program from the flash executes correctly, I assume that it is not a problem with the memory configuration. What could it be?

Hello,I have a question regarding VBUS sensing on STM32N6.First off, I found theGuide to USB development resources on STM32https://community.st.com/t5/stm32-mcus/guide-to-usb-development-resources-on-stm32/ta-p/790803I also read AN 4879. I want to use OTG1 of my MCU to establish a USB connection to my PC. The MCU is a self-powered device.Since it's a self-powered device, VBUS sensing becomes mandatory.In all ressources it is written that PA9 (or PB13) are used for VBUS sensing and are 5V tolerant. However, on the STM32N6, it seems that:- PA9 is not 5V tolerant- there is no mentioning of VBUS sensing functionality to this pin. The datasheet returns nothing if I search for VBUS.The Ref Manual 0486,Rev2 has a chapter 72.2.6 about VBUS det

The configuration:STLINK-V3SETConnected the two PCBs together via the three connectors (page 11).Attached jumper JP7 CAN_ON on MB1440 PCB (page 18).(STLINK-V3SET pages 17 & 23) & (NUCLEO-H723ZG page 37) & (Bootloader AN page 199) & (STM32H723 Manual page 143):Connected the T_CAN_VCC to 5V of NUCLEO-H723ZG; tried also the 3V3, same outcome.Connected the T_CAN_TX to the PD0 CAN1_RX pin 29 of CN9 connector of NUCLEO-H723ZG.Connected the T_CAN_RX to the PD1 CAN1_TX pin 29 of CN9 connector of NUCLEO-H723ZG.Reversed the PD0 and PD1, same outcome.NUCLEO-H723ZGConnected the boot0 pin to 3V3.Power cycled the Nucleo and verified that the bootloader is running and communicating via USB with the latest Cube Programmer.Power cycled the Nucleo and attempted to connect via CANBus. The Nucleo does not respond. The Cube Programme

Hi I am testing the Nucleo-L433RC-P board with a BlueNRG-2 BLE interface. I configured the setup, but the BLE device is not being detected in the ST BLE app. Look at pic, Any modifications require are not ?   

Hello,We are using the STM32N6 series MCU in our project and encountering issues during debugging. I’ve attached a screenshot of the error message we are seeing.We followed the steps outlined in this guide:https://community.st.com/t5/stm32-mcus/how-to-debug-stm32n6-using-stm32cubeide/ta-p/800547However, the code cannot be debugged from external flash (in dev boot mode).But, when we boot from flash (flash boot) and the debugger is not connected, the code runs as expected.Also, debugging from RAM with

Dear all,I'm implementing Over-the-air firmware updates for a board using the STM32N657 MCU.In the Appli, I download the new firmware binary over Wifi and store it to RAM at a fixed location in AXISRAM5 and 6. In order to flash the new binary to the OctoSPI Flash I prepend a "magic" header to the new firmware binary (still in RAM) and then restart the MCU using `HAL_NVIC_SystemReset`. Then, after this reset the FSBL checks the fixed location in RAM for the "magic" header. If present, it should flash the OctoSPI Flash with the new firmware binary using the ExtMem Manager (I cannot just flash directly from Appli because I use XIP and hence the Appli is running from OctoSPI in memory-mapped mode, preventing writes). I've done similar things with other MCUs and it worked perfectly fine.However, it looks like on the STM32N6, the contents of AXISRAM5 and 6 are not preserved across software resets. At least, checking the "magic" header in FSBL always produces randomly

Hello,I am implementing a sine wave generator based on the high-speed DAC3 of the G474.The DAC is in double-DMA mode and its conversions are triggered periodically  by a timer.Sample and Hold is disabled.The DAC is connected to an external pin by an OPAMP in the follower mode.What could be the reason for the downward slope shown on the picture? It is consistent even at low conversion speeds.Thank you for your help. 

Hello everyone on the forum.I have created a UART DMA receive program with Nucle-H723.This time it is working properly, but sometimes it does not work properly.DMA set up in normal mode on UART4 RX.DMA initialization function of UART.void UART_DMA_Init(UART_HandleTypeDef *huart) { UART_HandleTypeDef *pHuart = huart; memset(RxBuf, 0, UART_BUF_LEN); __HAL_UART_DISABLE_IT(pHuart, UART_IT_PE); __HAL_UART_DISABLE_IT(pHuart, UART_IT_ERR); __HAL_UART_ENABLE_IT(pHuart, UART_IT_IDLE); HAL_UART_Receive_DMA(pHuart, RxBuf, UART_BUF_LEN); }UART DMA receive processing function.