STM32 MCUs Products

Hi, I have set two ADCs on CubeIDE, for STM32G474CEU6 microcontroller, with DMA transfer. I am using ADC1 with timer 6 trigger out event and ADC3 with timer 7 trigger out event. The thing is, when I use timer 6 for both ADCs,  just for ADC1 or just for ADC3, they work just fine, but it seems that it is not capable of converting data using timer 7, as it never enters the dma conversion complete neither half conversion interrupt. I have also tried using different timers, but as long as they are not the same one  the ADC is not working. Both the reference manual and CubeIDE state that this timers are usable for these ADCs. Is this behaviour common? Should it be like that? As far as I understand, I should be able to use different sample frequency in different ADCs. In any case, why might this be happening? Thanks in advance.

I'm working with an STM32F412ZETx microcontroller and encountering an issue with the CAN2 peripheral. The transmit (Tx) functionality is working correctly, but the receive (Rx) interrupt via FIFO1 is not triggering at all.   CAN2 transmit works fine. I can see messages on the bus. same setup with CAN1 (Rx FIFO0) works fine. Is there anything specific I need to configure for CAN2 RX interrupts on STM32F412? Could the filter bank or SlaveStartFilterBank setting be causing this? Are there known limitations with CAN2 and FIFO1 on this device?

In the example ADF_AudioRecorder, the OutputClock.Divider is set to 4 (STM32Cube_FW_U5_V1.7.0\Projects\STM32U575I-EV\Examples\MDF\ADF_AudioRecorder\Src\main.c).But the datasheet RM0456 at page 1610 say: Fadf_proc_ck > 4 x FADF_CCKyWith Fadf_proc_ck = 4 x FADF_CCKy, this example doesn't respect the clock constraint.Who is correct ? the example or the RM ?

Hi All!I have a issue about SPI DMA communication on NUCLEO-H563 Board. Details are as follows.My Configuration of STM32CubeMx as shown in the figure1 and 2.figure1figure2I call the function of HAL_SPI_TransmitReceive_DMA(）, it comes to line 2212 of program and return HAL_ERROR then.I debug the program and find the value of hspi->

OK, I have a STM32L462RE Discovery Kit (apparently a.k.a. B-L462E-CELL1).I am trying to get its sole Demonstration application to work (STM32CubeExpansion_CELLULAR_V7.1.0\Projects\B-L462E-CELL1\Demonstrations\Nx_TCP_Echo_Client), but I can’t even tell how it is supposed to work. I see “TCP_Echo_Client” in its name, so I assume if I have a simple TCP echo server running on my workstation that if I do the appropriate port forwarding through my router along with the appropriate Windows Firewall settings, then I should see the B-L462E-CELL1 connect to my local TCP Echo Server. Is that correct?Further, I assume that in this file:STM32CubeExpansion_CELLULAR_V7.1.0\Projects\B-L462E-CELL1\Demonstrations\Nx_TCP_Echo_Client\NetXDuo\App\tcp_echo_client.cI should change TCP_SERVER_PORT from 7 to whatever TCP port my local TCP Echo server is running on, AND I should change the TCP_SERVER_ADDRESS IP_ADDRESS(5

Hi,it seems I have some general problem with the understanding of the SPI transmission with the STM32H5.I have an SPI, configured as master for transmission only. Initialisation and stuff is done by CubeMX-generated code, but the transmission shall be done more or less "manually". Means: I want to send 3x 1 byte by writing them one after an other into the related TXDR register.Now what I do NOT understand is, what flag do I have to wait for in order to see if a) I can write the next byte into the FIFO and b) see if all three bytes have been sent?From my understanding:a) can be achieved by waiting for the TXP-flag being set. As long as this is the case, I can write the next byte.b) can be achieved by waiting for the TXC-flag being set. As soon as this is the case, all data have been transmitted.However, there seems to be a dependency to the CR2-register. When I

Hello!I have a custom board with NAND flash connected. One of the DMA channels is used during write operations to move data from RAM to FMC buffer (mem-to-mem mode). The channel has low priority so theoretically it shouldn't interfere with other channels. Second DMA channel (same DMA controller) with high priority is intended to receive ADC data (two ADC channels with x8 oversampling). DMA channel works in circular mode non-stop, ADC is triggered by timer (1kHz, single conversion, discontinuous mode disabled, ADC_REG_OVR_DATA_OVERWRITTEN mode, 92.5 cycles per conversion).The issue is an ADC overrun during NAND write operation (mostly not every operation but with certain periodicity) what results in missing value as if ADC channels were swapped. Besides these DMA channels, two more DMA channels are used on same DMA controller but the latter ones aren't active at the moment of ADC overrun. If you simply move NAND DMA channel to another DMA controller, the overrun disappe

Question moved from this thread (a new question) Thank you very much for the solution. However, I’m still unclear about the core point. My main concern is that I need CAN files such that, when the code is flashed onto the STM32L4R9I-EVAL board, it should behave in the following way: upon receiving a CAN message, the board should either print something which is predefined or perform an action in response to that message. Could you please help me with this

Hi All,We are currently exploring microcontroller options to meet our system requirements. The system must support Ethernet communication at 1Gbps while simultaneously driving 24 GPIOs (12+12) with a single clock output at a speed of 38 MHz. All GPIOs should be updated on the rising edge of the clock signal and must be refreshed within half of the high duration of the clock signal, approximately 6ns.Additionally, the system requires high-speed external RAM to process data of approximately 1GB data. We have evaluated the GPIOs driving mechanism on one microcontroller, we encountered a bottleneck with the DMA clock source, as few clock cycles are required for proper DMA processing and updated GPIOs status by timer trigger event.We are seeking a microcontroller that meets these specifications and provides an efficient solution.Any suggestions will be appreciated.Thank you in advance.Jaydeep.

Dear Sir,We are facing an issue while bringing up the STM32 microcontroller (part number: STM32H747XIH6) using the internal SMPS.When we power the MCU through the LDO path, everything works fine, and we are able to connect to the STM32 via JTAG. However, when using the internal SMPS, the MCU does not respond and we are unable to establish a connection through JTAG.We have attached the relevant portion of the schematics for your reference.Could you please help us identify the issue with the internal SMPS configuration?  Best Regards,Samudralankaiah.

I am trying to periodically transfer data to the first byte of GPIOA (PA0-PA7) using DMA Channel 1 and TIMER1, but am hitting a transfer error immediately after enabling the DMA channel for transferring. * I can write to GPIOA->ODR using the CPU and I've confirmed the outpu

Hello,I would like to design a microphone array with up to 16 microphones. I want to use the stm32h7a3zi board which has a lot of peripherals.I was looking at the DFSDM interface, but with only 8 channels / 8 filters up to 8 pdm microphones can be handled.On the contrary, the SAI interface seems to be more promising. If I understood correctly, the SAI interface can be configured as PDM interface, and every SAI can handle up to 6 microphones. Moreover, the SAI interface supports synchronization between SAIs modules. Do you have suggestion/comments? 

Hello,Im working on a program which sends data from the ADC to the computer. My problem is that the data from my STM32H563ZIT6 is bad. I first noticed this from looking at the data sent from the computer and confirmed this by outputting the ADC data through the DAC. Attached is the output from a 50Khz sine wave. I am not sure what is causing this stair stepping pattern. For reference I have the ADC clock at 75Mhz, 6.5 cycle sample time, and triggered by a 1Mhz timer.I did notice that the data in the buffer seemed to be mostly shifted left 4 bits (though it never goes above 4095) or is missing the first 4 LSBs. 

I found an application note which goes in depth on DMA transfer speeds and clocking for F7 chips, but haven't been able to find anything similar for H7 chips. I have a few questions:How are each of the DMA controllers clocked on an H7xx chip? My assumption is MDMA is on the AXI clock and DMA1, DMA2 and BDMA are on the AHB clock. Is this correct?How would I go about calculating the worst-case latency for a memory-to-memory transfer by a given DMA controller from a given location in memory to another (in the same bank, or a different one)? How much latency does each domain link add, and do the H7 memory buses follow the same round robin allocation scheme described in the F7's application note? For example, if I were transferring 1 word of data from S

Hello, We use STM32H755 with a 25MHz crystal oscillator connected to OSC32_IN and OSC32_OUT OSC_IN and OSC_OUT pins. Probed on the bench, I see a sine wave with a DC offset and low amplitude. Can you comment if the attached waveform looks okay? My expectation was that the sine wave would swing from 0V to around 3.3V, and that there should be no added DC offset.  Thanks!

Hi,I´ve a application (with RTOS) where I do a FW update via the internal UART bootloader (BOOT0 pin method).After flashing is finished I set the Boot0 to GND and toggle the reset pin. The application starts, but I don´t get USART interrupts any more.After Power cycle interrupts are working again.Any idea?Best regards,Achim

Dear Community, i got two interconnected questions, as i want to build a measurement system that measures and generates sine signals and multi-sine signals with frequencies of up to 1 MHz. For this task i would like to have 10MSPS DAC and ADC acquisition. I thought about multiple ways of doing it and would like to hear your thoughts:Just do it all in analog and build a simple lock in amplifier and use an external  signal generator icThis would be the method i am currently using but it is fairly limited as it can only generate one frequency at a time or i would have to scale up the analog side.Use the build in ADCs and DACs to generate and measure the signals. The ADC of the G474 is 4MSPS at max res.  would be < 8MSPS in alternating trigger mode.Could i use the HRTIM to trigger all ADCs alternating to generate even higher sampling rates?Would the DMA be able to handle that? Do i tie all pins t

LTDC prevents CPU (of my MCU) from going into sleep mode. When i deactivate the LTDC clock, the CPU goes to sleep mode. LTDC interrupt is enabled trough IOC, without enabling of LTDC interrupt, screen remains black. I use the following MCU: STM32L4P5ZGT6P, IDE: STM32CubeIDE 1.11.2. Does someone know why this happens? An extract of my code:/* Clock of used hardwares on MCU is deactivated. */ __HAL_RCC_DMA1_CLK_DISABLE(); __HAL_RCC_I2C1_CLK_DISABLE(); __HAL_RCC_OSPI2_CLK_DISABLE(); __HAL_RCC_TIM6_CLK_DISABLE(); __HAL_RCC_TIM2_CLK_DISABLE(); __HAL_RCC_TIM3_CLK_DISABLE(); __HAL_RCC_USART2_CLK_DISABLE(); __HAL_RCC_UART4_CLK_DISABLE(); __HAL_RCC_UART5_CLK_DISABLE(); /*Suspend Tick increment to prevent wakeup by Systick interrupt. Otherwise the Systick interrupt will wake up the device within 1ms (HAL time base)*/ HAL_SuspendTick(); //CPU shall enter sleep mode after this instruction HAL_PWR_EnterSLEEPMode(PWR_MAI

Hi,We have a customized board with STM32F103, it measures water level and sends the data to a server, and then enters into Standby mode for 1 minute after setting up a RTC alarm for wakeup. Occasionally, we see wakeup failures. This happens randomly, it could be once after running for thousands of minutes, or could be once for hundreds of minutes.Any ideas ? And is there any way to check the reason why it happens?Any replies would be highly appreciated.Chao

Hi I am working on a project with STM32H730IBK6Q and STM32Cube IDE 1.16I am trying to use PA0_C as a GPIO, but the GPIO function is not connecting properly. PA0 is used an ADC, not as a GPIO, so from how I understand muxing there should be no conflict. But when I try to use PA0_C it reads a static value, even after I confirm connectivity. How do I properly configure my project to use PA0_C as a gpio? From the datasheet I got this cryptic instruction:Analog switch between ports Pxy_C and Pxy PA0_C, PA1_C, PC2_C and PC3_C can be connected internally to PA0, PA1, PC2 and PC3, respectively (refer to SYSCFG_PMCR register in RM0468 reference manual). The switch is controlled by VDDSWITCH voltage level. It is defined through BOOSTVDDSEL bit of SYSCFG_PMCR. If the switch is closed the switch characteristics are given in the table below.But nothing about what VDDSwitch is connected to physically or how to a

Hi ST Community, I’m working on a secure boot implementation for the STM32U3 series and need to replace the factory ROM bootloader with my custom secure bootloader. Here’s what I’d like to clarify: Can We Fully Remove the Factory Bootloader?The STM32U3’s ROM bootloader (System Memory) is in masked ROM, so is it even possible to erase or disable it completely?If not, what’s the most secure way to bypass it and ensure the MCU always boots from my custom bootloader in Flash?

Hello,I am using STM32G0B1cbt6. And I am using native bootloader to update firmware. But in some boards not able to update firmware, it is giving below error:And when we replaced the MCU then bootloader started working normally. The failure percentage is like out of 100, in 5 to 10 MCUs we are facing problem. What could be the reason? And how it can be resolved?This is a custom board.I am attaching the schematic below. Which running on standard 3.3V supply. 

I'm trying to get the DMA engine to trigger transfers on TIM8_CH1 (DMA Request Mapping:  Channel 7, Stream 2). However, it's not working. I verified that the TIM8_CC1 looked good by driving it to an alternate function output.  Then, all I changed was the DMA Request Mapping stream number: Channel 7, Stream 3, to select TIM8_CH2, and setup TIM8_CC2 instead of TIM8_CC1. Surprisingly this worked, and DMA is running as expected. I then setup both TIM8_CC1 and TIM8_CC2 with the same settings, routed both to GPIO pins using alternate function outputs, and looked at both signals on an oscope: They are completely identical. The only difference is setting up the DMA for TIM8_CH1 (stream 2) vs TIM8_CH2 (stream 3). For whatever reason, TIM8_CH1 (stream 2) doesn't work even though TIM8_CC1 is running. Any ideas?

Hi,I am testing the ECC on DTCM on the STM32H7A3ZI.  At start of day I initialize all of DTCM apart from a single test location.  I have a test which reads from that uninitialized location and successfully provokes the SRAM ECC interrupt, correctly reporting the address for the uninitialized location.  (I am following application note AN5342).However, I am finding that the same ECC error is raised in other circumstances, when I am confident that my code is not reading the test location.  This happens when the IDE is not connected, so it is not the IDE which is reading that location.I have another test that provokes flash ECC errors, and it is currently the code of this test that somehow provokes the SRAM ECC error as well as the flash ECC error.  However I don't think this code is reading the uninitialized location (and I have also seen other code provoke the problem).  The address reported in the FAR register is always that of my u

Does anyone know if the PGA OpAmp in the STM32 has the ability to interface with a differential input - like a Strain Gauge Wheatstone bridge?  I'm not convinced its going to work because my signal is going to swing +/-50mV, and the OpAmp does no look like it can handle a differential input.  There's probably some jiggly pokery that can be done to condition it externally, just wondered if anyone has any experience before I go down that route myself.