Input Samplerate of STA309A

[schwimmen]

Posted on October 17, 2016 at 16:49

Hey there,

i have problems to choose the right input setting of the STA309A.

My current input is I2S with 48 samples at 512*fs.

The sites 22-25 of the datasheet are a bit confusing. In CONFA i can choose a MSC e.g. of 48 samples with 512*fs. But at page 25 i only can choose a maximum of 64*fs for I2S input sound formats. What is the difference between those registers and settings?

Which configuration now is the right one? I have a XTI input of 24.576 MHz at the ADC's and the DSP.

Greetings!

[Nickname1623_O]

Posted on October 18, 2016 at 03:50

hi ,

according to your info about master clock , it's 512 FS (24.576Mhz ) , then looks like that your sampling frequency is 48Khz , and your bit clock is not matching with 48*Fs , it should be 64 Fs , then your byte length was 64 bits , then you should choose 0000 for SAI bits .

Thanks

YT

[schwimmen]

Posted on October 20, 2016 at 03:11

hi,

thank you for answering so fast!

My dsp still isn't working.

Now i found out, that when i select binary output except of ddx ouput, the STA outputs a duty cycle of 50% which means: ''Detects loss of input MCLK in binary mode and will output 50% duty cycle.''.

What is MCLK - is this the frequency on the XTI (pin 20), or does the master clock belong to PLL (filter_pll - pin 21)?

My circuit consist two four channel ADCs and the STA309A. All get the 24.576MHz clock from the same crystal oscillator, so i can choose different sample frequencies. I tried out another audio format (e.g. 24-bit MSB left-justified) to proof, if the ADC work fine (they do). But i still have no output at the sta.

Is there maybe the configuration of the STA wrong?

Thanks,

Greetings!

mE

[Nickname1623_O]

Posted on October 20, 2016 at 09:12

Hi Me ,

the Master clock could be the clock that you fed to ADC , since ADC may provide LRCK and BICK to system , then I2S clock must be synchronized with Master clock for STA309A , otherwise you will hear pop corn noise .

if the setting for ADC is 48Khz LRCK, and 3.072Mhz Bick, you need also change the STA309A input setting in 0x00 register MSC bits , it's 256FS in default , for 512FS ,48Khz , the value of MSC bits should be 001.

Thanks

YT

[schwimmen]

Posted on October 22, 2016 at 00:49

Hi YT,

that is, what i did. But i still can't get out any signal. Isn't the clock synchronisation the right setting of registers 0x00 and 0x01?

I said, that in PWM setting the STA gives out a 50% duty cycle signal. How i can fix the problem of a loss clock? I can't find any wrong setting of the registers and i checked my board if there e.g. is a short cut or if the STA doesn't recieve a signal on the XTI pin, but everything is fine.

Shall i send you my register configuration?

Thanks,

mE

[schwimmen]

Posted on October 30, 2016 at 18:23

hi there,

can somebody else help me with me loss clock of MCKL? I've tested everything on my board and the register settings.

What is MCKL and how i can find out, why its not working (measuring)?

Thanks,

Greetings,

mE

[Nickname1623_O]

Posted on October 31, 2016 at 03:22

Hi Me ,

you can refer to schematic in datasheet  page 18 for MCLK connection, it's XTI input. below link is latest datasheet.

http://www.st.com/content/ccc/resource/technical/document/datasheet/97/41/d6/a4/6b/2a/40/b9/CD00169555.pdf/files/CD00169555.pdf/jcr:content/translations/en.CD00169555.pdf

and STA309A default PWM output is in ternary modulation mode ,if the mute bit had been set , the output will be stopped , please adjusted your volume and mute setting according to page 36 in datasheet .

by the way, you can download Audioworkbench software from ST website to get quick access of STA309A registers.

Thanks

YT

[schwimmen]

Posted on October 31, 2016 at 21:03

Hello YT,

thanks for answering!

I now got sound out of the dsp. But only on channel 1 and ch 8.

on ch 1 i can select every input channel i want from i2s. but ch 8 is fixed.

my setting now is: 192kSamples, (128*fs).

things i've measured:

XTI = 24.576 MHz,

CKOUT = 28.8 to 29 MHz

PWM Output ~ only 227 kHz (@ double speed setting at config F register)

i like the STA309A very much - it's so a powerful DSP and looks easy to handle.

how i can fix this problem? is it the PLL circuit? e.g. i cannot measure any frequence on it. or must the PPLB pin set to high to enable PLL? (PLLB set to low in the reference schematic).

or maybe the STA309 cannot handle 24.576 MHz?

Thank you!

Greetings,

mE

[schwimmen]

Posted on November 01, 2016 at 11:52

edit:

my register setting:

0x00: 0x13

0x01: 0x00

0x04: 0xff

0x05: 0x40

0x07: 0x4e (must have i2s AND mclk fail check disabled to get output)

[schwimmen]

Posted on November 08, 2016 at 17:28

Can i maybe get help somewhere else?

I cannot believe it's so a big problem, the STA309A is not working =(

Is there another audio processor with eight channels mixable?

Thanks,

mE

[Nickname1623_O]

Posted on November 15, 2016 at 09:30

hi ME,

STA309A can handle 192Khz sample rate .

according to your hardware configuration, please make sure your bit clock is 12.288Mhz ,due to it's 64FS .

and your clock output frequency is strange , please check your  PLL networks parameters , is it aligned with ST recommended application circuitry .

by the way, please down load APWorkbench from ST website, this tools will help you to initialize STA309A properly .

Thanks

YT