How to properly read many ADC channels that are not consecutive with DMA?

[aurelien23]

Hello,

on SPC564B74 I want to read ADC0 channels 35 to 48, 51 to 54, 64, 72 and 80, and on ADC1 channels 0 to 15 and 32 to 38, so not consecutive channels.

I started from the SPC56ECxx OS-Less ADC Test Application example in SPC5 studio 5.8.1.

Each call to adcStartConversion to address a group are separated using a basic osalThreadSleepMilliseconds(100) but I always have one or more channels (usually the first of a group, ADC0 ch35 and adc1 ch0) that is correctly converted on the first call only (and remains to the same value. observed in pls udestk watch window).

I also tried a system tick based method to separate conversions without success.

Can I please get a explanation how to correctly organise the conversions (manual edma reconfiguration?). The DMA is configured in the generated code each time a conversion start is called so what is missing?

The pin wizard and configuration are ok to me, see attached.

int main(void) {

 /* Initialization of all the imported components in the order specified in

   the application wizard. The function is generated automatically.*/

 componentsInit();

 /* Starts the ADC drivers.*/

 adcStart(&ADCD1, NULL);

 adcStart(&ADCD2, NULL);

 /* Normal main() thread activity. */

 while (TRUE) {

// ADC0

osalThreadSleepMilliseconds(100);

adcStartConversion(&ADCD1, &adc0_group_cfgadc0_ch64,samplesADC0_ch64, 1);

osalThreadSleepMilliseconds(100);

adcStartConversion(&ADCD1, &adc0_group_cfgadc0_ch72,samplesADC0_ch72, 1);

osalThreadSleepMilliseconds(100);

adcStartConversion(&ADCD1, &adc0_group_cfgadc0_ch80,samplesADC0_ch80, 1);

osalThreadSleepMilliseconds(100);

adcStartConversion(&ADCD1, &adc0_group_cfgadc0_ch35to48,samplesADC0_ch35to48, ADC0_GROUP_CFGADC0_CH35TO48_BUF_DEPTH);

osalThreadSleepMilliseconds(100);

adcStartConversion(&ADCD1, &adc0_group_cfgadc0_ch51to54,samplesADC0_ch51to54, ADC0_GROUP_CFGADC0_CH51TO54_BUF_DEPTH);

// ADC1

osalThreadSleepMilliseconds(100);

adcStartConversion(&ADCD2, &adc1_group_cfgadc1ch0to15,samplesADC1_ch0to15, ADC1_GROUP_CFGADC1CH0TO15_BUF_DEPTH);

osalThreadSleepMilliseconds(100);

adcStartConversion(&ADCD2, &adc1_group_cfgadc1ch32to38,samplesADC1_ch32to38, ADC1_GROUP_CFGADC1CH32TO38_BUF_DEPTH);

 }

}

thank you for your support

[Giuseppe DI-GIORE]

Hello,

the ADC driver has been implemented to manage DMA reads only with consecutive ADC channels.

In order to use DMA with non consecutive ADC channels, yuo have to modify the ADC driver as following:

• use different DMA channels for non consecutive ADC channel
• use scatter-gather functionality of eDMA (linking multiple channel together)

Regards,

Giuseppe

[CCOLL.2]

Hi,

Do you have an example of modified ADC driver ?

Could you give me more details about "scatter-gather functionnality of eDMA" ?

(I quickly tried to do such modification but I did not reach to modify the eDMA part to have it working)

Thanks,

Christophe

[aurelien23]

Hello,

it didn't helped to use a different DMA channel. I found a simple workaround: I set buffer depth to 2, making the ADC reding each channel twice, and I copy the sampled value manually from ADCD2.adc_tagp->CDR[0].R & 0x00000FFF;

I had the same problem with the latest RLA drivers from SPC5 Studio 6.0, and it always concerned the ADC1 channel 0 only, so I still think there is some special behaviour on this input.

Thank you for your support in 2020. I hope your team will expand like the nomber of community questions does ;)

Regards,

Aurélien