PIT, multiple interrupts at different times
Hello all.
I'm playing around with the PIT interrupts and im finding that after setting up 3 seperate timers with different interrupt rates with the same priority setup in the IRQ Component rla. It's only constantly interrupting the PIT with the lowest timer.
for example, in my case PIT 2 is the only one getting interrupted. is there an issue with multiple TIE being set ?
Setup:
/* PIT clock enabled. */
SPCSetPeripheralClockMode(92, SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
PIT.PITMCR.R = 1;
//clk @ 48Mhz
//////////////////////////////////////////////////////////////////////////////
//PIT 1
PIT.CH[1].LDVAL.R = 60000000;
PIT.CH[1].CVAL.R = 60000000;
PIT.CH[1].TFLG.R = 1;
PIT.CH[1].TCTRL.R = 3;
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//PIT 2
PIT.CH[2].LDVAL.R = 48000000;
PIT.CH[2].CVAL.R = 48000000;
PIT.CH[2].TFLG.R = 1;
PIT.CH[2].TCTRL.R = 3; //////////////////////////////////////////////////////////////////////////////
// PIT 3
//CAN_DELAY_GLOBAL
PIT.CH[3].LDVAL.R = 58000000;
PIT.CH[3].CVAL.R = 58000000;
PIT.CH[3].TFLG.R = 1;
PIT.CH[3].TCTRL.R = 3;
