SPC58ECx wakeup from standby using WKUP Pin

[R PV]

Posted on September 02, 2017 at 17:40

hello team,when i wakeup from standby mode always system reset was generating.My SW not jumping to address what i mentioned in CADDR register .when i debug the issue found 'F_FCCU_HARD' Flag was enable after wakeup. is there is any method to disable this Flag permanently? if yes.please share some sample code to handle FCCU Module?

Thanks in advance.

[Erwan YVIN]

Posted on September 04, 2017 at 10:34

Hello ,

we have no example for SPC58ECx wakeup from Standby mode.

Anyway , there is an example in SPC5Studio Appwizard

SPC560Dxx OS-Less STANDBY SRAM Test Application for Discovery

you should put some functions in SRAM.

  Best regards

             Erwan

[R PV]

Posted on September 05, 2017 at 08:42

Hello Erwan,

I'm not using SPC5studio ,can you share some examples of how to handle standby mode of SPC58 series uC .I don't need any cyclic task in standby mode,just want to enter into standby mode and exit using wakup pin and jump to address mentioned in CADDR register.

[Erwan YVIN]

Posted on September 05, 2017 at 09:32

Hello Varma ,

There is an interesting chapter about the Standby Mode

Restart from Stand-by RAM with the Flash powered off

This feature makes it possible to wake-up the micro-controller from the Stand-By mode and

let the Boot CPU and the Security Module CPU restart directly from the RAM, while the

Flash is powered off (e).

In case of restart from stand-by with the Flash powered-off, only the Boot CPU and the HSM

CPU (if enabled after Stand-by via DCF) shall be woken up. Other CPUs shall be kept under

reset.. The restart after Stand-by from RAM is made possible by using the Mode Entry

registers:

• ME_CCTLn => to set up the processor status (ON/OFF) for each mode (note: the

register associated to the Security Module CPU can be written by the Security Module

CPU only)

• ME_CADDRn => to set up the processor reset vector (note: the register associated to

the Security Module CPU can be written by the Security Module CPU only)

• ME_<mode>_MC => to set up whether the Flash is ON or OFF

Anyway, you can use for SPC56xx

but there is no CADDR & CCTL registers

https://github.com/microwan/spc560dxx-demos/tree/master/SPC560Dxx%20OS-Less%20STANDBY%20SRAM%20Test%20Application%20for%20Discovery

 

  best regards

            Erwan

[Erwan YVIN]

Posted on September 06, 2017 at 09:23

Yes , if the flash is power down it should generate a reset.

there is some options to keep the flash alive.

ok you can put your function in SRAM

__attribute__ ((section ('.codeinram'))) void gotoStandbyMode(void) {
WKUP.WISR.R = 0x00000008;//Clear interrupt flag
if ((ME.GS.B.S_CURRENTMODE < SPC5_RUNMODE_RUN3)
 || (ME.GS.B.S_CURRENTMODE > SPC5_RUNMODE_RUN0)) {
 if (OSAL_FAILED == halSPCSetRunMode(SPC5_RUNMODE_STANDBY)) {
 SPC5_CLOCK_FAILURE_HOOK();
 }
 }
}
__attribute__ ((section ('.codeinram'))) void gotoRunMode(void)
{
 if (OSAL_FAILED == halSPCSetRunMode(SPC5_RUNMODE_DRUN)) {
 SPC5_CLOCK_FAILURE_HOOK();
 }
}
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Best regards

Erwan

[R PV]

Posted on September 11, 2017 at 16:44

Hello Erwan,

I kept flash @normal mode in standby mode. and whenever Wakeup event occurs my SW starts at CADDR address and  hangs in clock module.

DRUN >RUN not happening...after wakup...?

(MTRANS==1)

In standby mode ,IR OSC is ON,

FLAON is Normal.

[Erwan YVIN]

Posted on September 13, 2017 at 09:21

Hello Varma ,

You clock config is not correct.

1) check your PCTL and ME_PSx registers to check if some peripheral is ON and prevent from the transition

2) check your IMTS registers

check the chapter 11.6.2.2

Anyway , i am checking with experts if Application Notes are existing on the subject.

           Best regards

                     Erwan

[Erwan YVIN]

Posted on September 13, 2017 at 10:29

Hello Varma ,

Could you confirm your CADDR from Flash or SRAM Standby ?

if you choose SRAM Standby (24k,224k), do not forget to configure PCU_PCONF1-2-3

            Best Regards

                     Erwan

[R PV]

Posted on September 15, 2017 at 12:50

Hello Erwan,

I'm using Flash address (my start address) in CADDR .not SRAM address.

Thru  debugging I found XOSC going unstable after wake-up.thats way control halted at Clock module.because PLLs values derived from XOSC.

then I changed my system completely to IROSC to generate PLLs and CAN clock.

Then system working fine after wakup without halt in clock module.

But whenever I tried to re-enter standby after wakeup ,then system enters into halt(stop) Mode(observed thru debugger status) and wakeup was not happening.only way to come out is RESET.

Can you suggest me some solutions .

Is still clock is not configured properly?

Can you share some application notes and example configuration for my requirement?

ThanQ