Solved
SPI Tx stucks on 1MHz clock
Hello All,
I'm usin SR6P3 ARM mcu. I have to implement a simple SPI communication with StellarSDK.
When send/receive starts the communication stucks in a while cycle where the code checks Tx queue busyness.
while (queue->tx_busy == SPIQ_QUEUE_TX_BUSY) {
;
}
Never comes out from this while. The clock is 1MHz.
But if I set the clock lower like 50kHz, then the communication is good.
This is the pin configuration:
/*===========================================================================*/
/* SPIQ 0 */
/*===========================================================================*/
/* SPIQ0 CLK - PJ12 */
#define SPIQ0_CLK siul2_iopack(SIUL2_PORT_J, SIUL2_PAD_12)
#define SPIQ0_CLK_CFG (SIUL2_MSCR_IO_SSS(0x0B) | \
SIUL2_MSCR_IO_OERC_STRONG | \
SIUL2_MSCR_IO_ODC_PUSH_PULL | \
SIUL2_MSCR_IO_SMC | \
SIUL2_MSCR_IO_ILS_AUTO | \
SIUL2_MSCR_IO_IBE)
/* SPIQ0 SOUT - PK13 */
#define SPIQ0_SOUT siul2_iopack(SIUL2_PORT_K, SIUL2_PAD_13)
#define SPIQ0_SOUT_CFG (SIUL2_MSCR_IO_SSS(0x0E) | \
SIUL2_MSCR_IO_OERC_STRONG | \
SIUL2_MSCR_IO_ODC_PUSH_PULL | \
SIUL2_MSCR_IO_SMC | \
SIUL2_MSCR_IO_ILS_AUTO | \
SIUL2_MSCR_IO_IBE)
/* SPIQ0 SIN - PJ11 */
#define SPIQ0_SIN siul2_iopack(SIUL2_PORT_J, SIUL2_PAD_11)
#define SPIQ0_SIN_CFG (SIUL2_MSCR_IO_SSS(0x00) | \
SIUL2_MSCR_IO_ILS_TTL | \
SIUL2_MSCR_IO_OERC_STRONG | \
SIUL2_MSCR_IO_FILBYPASS | \
SIUL2_MSCR_IO_IBE)
#define SPIQ0_SIN_IOMUX 971u
/* SPIQ0 SIN MSCR.SSS = 0x00 - PJ11 (MSCR Register 971) */
#define SPIQ0_SIN_IOMUX_CFG 1u
/* SPIQ0 CS0 - PJ8 */
#define SPIQ0_CS0 siul2_iopack(SIUL2_PORT_J, SIUL2_PAD_8)
#define SPIQ0_CS0_CFG (SIUL2_MSCR_IO_SSS(0x08) | \
SIUL2_MSCR_IO_OERC_STRONG | \
SIUL2_MSCR_IO_ODC_PUSH_PULL | \
SIUL2_MSCR_IO_SMC | \
SIUL2_MSCR_IO_ILS_AUTO | \
SIUL2_MSCR_IO_IBE)
#define SPIQ0_CS0_IOMUX 969u
#define SPIQ0_CS0_IOMUX_CFG 2u
And this is the SPI config:
spiq_pcs_default_level(&spiqd_0, SPIQ_PCS_0, SPIQ_SIGNAL_LEVEL_HIGH);
spiq_start(&spiqd_0);
queue_SBC_PFS273 = spiq_queue_allocate(&spiqd_0);
tac_SBC_PFS273 = spiq_tac_allocate(&spiqd_0);
spiq_queue_mode(queue_SBC_PFS273, SPIQ_QUEUE_MODE_PRIO_5);
spiq_queue_mode(queue_SBC_PFS273, SPIQ_QUEUE_MODE_TX_SYNCHRONOUS);
spiq_queue_mode(queue_SBC_PFS273, SPIQ_QUEUE_MODE_TX_CPU);
spiq_queue_mode(queue_SBC_PFS273, SPIQ_QUEUE_MODE_RX_SYNCHRONOUS);
spiq_queue_mode(queue_SBC_PFS273, SPIQ_QUEUE_MODE_RX_CPU);
/*Trasfer control registers setup*/
uint32_t leading_delay = spiq_tac_mode_set_delay(tac_SBC_PFS273, SPIQ_TAC_LEADING_DELAY, 800UL);
uint32_t trailing_delay = spiq_tac_mode_set_delay(tac_SBC_PFS273, SPIQ_TAC_TRAILING_DELAY, 800UL);
uint32_t inter_word_delay = spiq_tac_mode_set_delay(tac_SBC_PFS273, SPIQ_TAC_INTER_WORD_DELAY, 200UL);
uint32_t next_frame_delay = spiq_tac_mode_set_delay(tac_SBC_PFS273, SPIQ_TAC_NEXT_FRAME_DELAY, 200UL);
effective_baud_rate = spiq_tac_mode_set_baud_rate(tac_SBC_PFS273, 50000UL, SPIQ_TAC_BAUD_DOUBLE_OFF);
spiq_tac_mode(tac_SBC_PFS273, SPIQ_TAC_CLOCK_INACTIVE_LOW); //(CPOL = 0)
spiq_tac_mode(tac_SBC_PFS273, SPIQ_TAC_CLOCK_PHASE_HIGH); // (CHPA = 1)
spiq_tac_mode(tac_SBC_PFS273, SPIQ_TAC_SHIFT_MSB_FIRST);
spiq_tac_mode(tac_SBC_PFS273, SPIQ_TAC_FRAME_SIZE_32_BITS);
spiq_tac_mode(tac_SBC_PFS273, SPIQ_TAC_SW_TRIGGER_ENABLE);
spiq_tac_mode(tac_SBC_PFS273, SPIQ_TAC_DATA_IN_RXFIFO);
spiq_tac_mode(tac_SBC_PFS273, SPIQ_TAC_CRC_DISABLE);
spiq_tac_set_pcs(tac_SBC_PFS273, SPIQ_PCS_0);
spiq_tac_mode(tac_SBC_PFS273, SPIQ_TAC_CONT_PCS_DISABLED);
Does anybody know what should be the problem. Thanks.