Using SPC582B chip with only 64 pins, will it be possible to use JTAG to send traces ?

[CCOLL.2]

Using SPC582B chip with only 64 pins, the nexus interface pins will not be available.

Does this mean that there are no trace possibilities ?

[Erwan YVIN]

hello ,

JTAG port is well present for classical debug.

we are using PLS UDE.

"All NXMC input functionality is controlled through the JTAG port in compliance with IEEE

1149.1 (refer to Section 63.5.1: IEEE 1149.1 (JTAG) Test Access Port for details). A

separate JTAG TAP controller is instantiated within the NXMC. Table 956 describes the

JTAG pins."

Best Regards

Erwan

[CCOLL.2]

Hi Erwan,

Thanks for your answer.

In fact, I'm not aware of the JTAG feature. So, to precise my question, as we do not have Nexus pins available, will it be possible to have traces and to do code coverage and profiling with only JTAG pins?

Rgds,

Christophe

[CCOLL.2]

Hi,

To complete my question, on 64 pins chip, I agree that we have access to JTAG pins but we don't have access to the Nexus auxiliary port pins.

I understand that there is the SPU HW bloc which goal is to give an interface between JTAG pins and some Nexus HW blocs inside the chip. But we cannot use all the debug features.

So, if I use the 64 pins chip and a probe like PLS UAD2Pro, can I use Nexus traces in order to do SW code coverage and code profiling ?