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philippe26
Visitor II
June 17, 2019
Question

JTAG pin interface on STA8090FG

  • June 17, 2019
  • 1 reply
  • 680 views

Hi,

The datasheet of STA8090FG only list in table 5 the test/emulated dedicated pins but there is no information how to use the pins.

Is it IEEE 1149.1 compliant ?

What are the interface timings ?

Does TRSTn only reset the JTAG logic and must be left to ground during normal operation ?

Thanks,

Regards.

    This topic has been closed for replies.

    1 reply

    Tesla DeLorean
    Guru
    June 17, 2019

    I'd imagine it functions like the JTAG on every other ARM9 based core from the last few decades. Pretty sure the eval board exposes it to a header, and has a schematic.

    https://www.st.com/resource/en/data_brief/dm00373428.pdf

    Doesn't Thales have a business account and contacts directly into ST they could use to find an FAE? They'd probably be able to supply an IBIS file too.

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