STOTG04E Timing constraints of OE_TP_INT/ signal and Data paths. Setup time vs Bus turnaround time.

[not_a_gamer]

Product: STOTG04E USB OTG LS/FS PHY

What is the difference between the idle and output state when the oe_tp_int/ signal is high?

My rec_bias_en bit from the Control Register 3 is low. (i.e transmit bias circuitry is disabled during the receive mode), and my data signals (DAT_VP and SE0_VM) are delayed by (5 to 10) ns with resepect to OE_TP_INT/ signal.

Could this cause any USB compliance failure?

References: Data sheet Figure 8 and Figure 9.

Do inform if any relevant details are required.

Thanks.