Understanding VALID/READY handshakes (AXI/AMBA)
Hi everyone! I’ve been diving into the AXI4 protocol for a small design exercise, and while I’m making progress, I’m still trying to build a solid intuition for the VALID/READY handshake, especially on the less 'visible' channels like the Write Response (B channel)...
I’ve spent quite a bit of time with the official specification, but there’s a difference between reading the rules and actually 'seeing' how the handshakes play out in a high-performance design. for those of you who work with ARM buses or SoC design professionally, what was the 'aha!' moment for you?
did you find it most heloful to strictly study the timing diagrams, or was it more about building small simulation testbenches and observing how the bus stalls when READY is de-asserted??? I’m trying to avoid getting overwhelmed by the sheer volume of the spec and instead focus on a practical, design-first understanding. Any advice on learning strategies or common pitfalls to watch out for would be incredibly helpful. Thanks!
AMBA AXI overview (ARM):
https://developer.arm.com/documentation/ihi0022/latest/Introduction to AMBA AXI (learning guide):
https://developer.arm.com/documentation/102202/latestSTM32 + ARM architecture background:
https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html