Reading both ADS8350 ADC serial channels with SPI or DMA

[physicist]

Hello,

I have the TI ADS8350 and want to read both channels in parallel. They support SPI, but I can not figure out how to setup the dual SPI for this. Another way would be to use DMA, could someone point me in the right direction. I am using SMT32F412.

Thanks.

 

[Andrew Neil]

So this: https://www.ti.com/product/ADS8350 

Do TI have any suggestions/recommendations on this?

https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum

In SPI terms, Looks like it has a single SCLK, two MISOs, and no MOSI:

So the start of the read is triggered purely by /CS:

So maybe try:

• Use one SPI as Master, to generate the clock
• Use another SPI as Slave, clocked by the Master

You'll need to manually control /CS anyhow to get the t_CONV timing

 

PS:

You may also need to feed the /CS back into the Slave...

 

[physicist]

And if I want to have a specific acquisition time should I use one /CS for slave SPI and second for ADC because with this ADC the acquisition time is controlled by the /CS pin.

[Andrew Neil]

I would think not: there should be just one /CS - that's what synchronises everything.

 

Looking at it again, it seems that  t_CONV isn't (just) a time - it's a number of clock cycles.

You should be able to get that by the Master clocking-out a 16-bit value (just a dummy that gets ignored).

Again, this is all about  the TI chip; so TI would be experts and they would be the ones to ask.

https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum 

None of this is specific to STM32.

[MasterT]

I interfaced ads8354 to stm32h743, using one spi as master, and another as a slave 2-line rx only. The beauty of H7 is that it can drive CS line by spi in master /dma mode.  F4 & F7 don't have this future, so if you can't switch project to h7m than I'd recommend config two spi as slaves driven by two linked timers. First timer -gated generates 16-clock for SCLK, and second drives CS and defines sampling rate.

[physicist]

Thanks, I am forced to use the F4. So I should confing 2 spi slaves that will just read with first gated timer being trigered by some ITR, and second timer for CS, and I get the ITR from its output compare? 

[Andrew Neil]

You could still try the Master + Slave, and get the Master to give the 16 clocks as suggested?

Should be easy enough to try ...

 

PS:

The F4 does have a kind of hardware /CS control:

https://www.st.com/resource/en/reference_manual/rm0402-stm32f412-advanced-armbased-32bit-mcus-stmicroelectronics.pdf#page=809

Maybe that could be made to work?

 

There's also QUADSPI ...