TVS selection for stm32u0 SWD

[sb_st]

Hi! Apologies up front that I realize this is a relatively entry-level question - I am trying to build some experience selecting TVS diodes. My design uses a TagConnect footprint for SWD to an stm32u0. I intend to run the MCU at 1.8V, though I'm unsure how much that matters. 

I found this very excellent Application Note from ST, and in section 3.6 there are even some parts provided for this exact use. When I look at the datasheet for the ESDALC6V1W, however, it seems like it's showing a working voltage of 3V, with a breakdown voltage of 7.2V. 

I'm confused by this - it seems like a typical working voltage for a 3.3V MCU would want to be >3.3V. If I understand correctly, a working voltage of 3V in such a system would distort the SWD data signals a bit (though, as I understand it, this would work fine if we're operating the MCU at 1.8V).

More confusing to me is that the breakdown voltage of 7.2V seems much higher than the Absolute Maximums listed for most GPIOs (particularly the NRST line, which seems to have an absolute maximum tolerance of 4V in the datasheets I've looked at). 

I'm wondering if I am misunderstanding the use case in this application note (maybe this example presumes an MCU with different Vin/max toleranaces?) What I'm more concerned about is that I don't understand something fundamental about choosing these parts. 

For the U0 line, I assume I should be looking for TVS diodes that have a working voltage of >=3.3v, with a clamping voltage of 4V (if I'm being conservative and considering the NRST pin, which seems to have the lowest tolerance). Am I understanding that correctly?

Thank you! And again, sorry, I realize this is not exactly specific to ST, and is more a general engineering question. I'm still learning :)

 

[Peter BENSCH]

Yes, the application note largely refers to the widely used VDD of 3.3V. However, you can find the values required for the ESD diodes in the respective data sheet: SWDIO/SWCLK are FT_xxx pins that can tolerate a maximum VDD+4V, i.e. 5.8V at 1.8V. You could possibly consider the HSP051-4M10 for this.

Hope that helps?

Regards
/Peter

[sb_st]

Thank you! That does help a bit, though - in the interest of trying to double-check my understanding of things - if I read the datasheet for that part, it lists a clamping voltage of 13V for IEC61000-4-2, despite having a breakdown voltage of 5.8V. If I understand correctly, even though the diode *starts* shunting near the absolute max for the SWDIO/SWCLK pins, it would still not clamp until much later, 13V, which I think is detrimental for the MCU...is that correct?

(again, I'm trying to shore up my understanding here). 

Additionally, am I right in understanding that NRST is actually only tolerant to 4V? So all of the above is moot anyway given that the NRST pin would be harmed? 

I think what I'm trying to reconcile is what seems like a gap between the hard math of the datasheets and what I see being used in practice. Like, the ESDALC6V1W is obviously specifically intended to be used for this purpose in 3.3v systems, but again NRST says its max tolerance is 4V irrespective of VDD, and the clamping voltage of that part at 16A is quite a bit higher than any of the max tolerances I find in datasheets. I feel like I'm missing something critical that squares all this, almost-assuredly due to my lack of experience...

Thank you again!