Is this normal behavior for the L6491 Smart Shutdown signal/system?

[EWill.3]

Using 2xL6491 in a full H-Bridge inverter for a PMDC motor, PWM switching frequency is 32kHz. With the smart SD threshold set low to verify the functionality, we see what appears to be skipped PWM pulses most likely due to the shutdown system blocking the gate driver outputs. However, it does not appear the SD signal is driven each time and that there's a "recovery time" almost for this signal. Given the RC filtering on the SD signal in our system, the gradual rise back to high is understood, but why the SD signal isn't driven down to 0V with each skipped pulse or each "batch" of skipped pulses doesn't make sense.

Would anyone be able to help us understand this behavior?

[Cristiana SCARAMEL]

Hello @EWill.3​ and welcome to the ST Community.

About the attached screenshot:

• yellow trace is the SD/OD pin voltage
• blue light trace is a gate driver output (LVG?)

The SD/OD pin is pulled-down when the integrated comparator is triggered, that is when the CP+ voltage rise the CP- voltage (refer to Figure 6 in the L6491 datasheet).

You have to monitor these voltages to verify if the smart shutdown function is properly working.

Let me know if these info are useful to you.