STEF12H60M(A) eFuse - Adding capacitance onto CS pin (23), to avoid tripping on transients

[OwenR]

(Note: I raised a support case about this, but it was closed, and requested that I ask in here). I wondered if there are any further details / anyone is aware of any issues with adding a capacitor from CS in (23) to ground (so in parallel across the external CS sense resistor), in order to prevent short-transients from causing the device to trip? There doesn't seem to be anything mentioned in the datasheet about doing this (Which is also very-vague about what amount output capacitance is necessary, and there doesn't seem to be any additional design info / spreadsheet tools that some recent competitor devices have - and which also have additional transient-suppression ability). I have found that adding a 4.7nF capacitor across the R_CS resistor value, would stop a 2.5V dip for 500us of Vout (as Vout rose above 8V into the non purely-resistive load of a commercial receiver unit), from causing the STEF12H60M to trip. Whilst increasing the output capacitance to 1500uF would also generally achieve this, there is then a large delay for this to discharge, when disabled with load removed, whilst an error condition is flagged / before Vout is low-enough for restart to be achieved. Also, increasing the Cout value much further, can also result in a trip with no-load, due to initial current surge into that, and so necessitates a much larger current-limit that is too high for the present application. And doing that still doesn't allow start-up into an electronic Constant-current etc. load (even with slowest start / slew-rate settings), for initial testing. Whereas, increasing the capacitance on the CS pin, much further (to around 10uF), has been found to allow start-up at full max load current into an electronic load - Rather than having to use Power-Rheostats, that are now virtually all obsoleted. But I was concerned that delaying the protection that much, could potentially cause failure of the device if the internal Power-MOSFET overheated, before it shut-off - Although I have tried deliberately shorting the output and not found any noticeable differences in the amount of energy in the spark from this / any noticeable thermal rise of the device from repeated attempts of this (with the device set for a just under 10A current-limit, and a 20A PSU limit, at least). So I wanted to check for any potential problems with adding this much capacitance? - In practice, the device should not normally trip and if it does it would most likely be due to a permanent non-recoverable fault with the load, so we'd have to repair the whole unit it was in. TIA, Owen

[AScha.3]

Owen, can you describe short 

- what you doing

- what it should do

- what is wrong , maybe with scope pic , to see current /time

[OwenR]

I'm trying to enable the STEF12H60MA, with a (non-resistive) load connected that itself needs to have its (mechanical) on/off switch always switched-on.
But intermittently (especially with all capacitors in system fully-discharged), the STEF12H60MA trips, due to transient current peak exceeding the set current limit (already quite-high, at rating of the connector)
- Often repeatedly, every second, for > 10s.
However, disabling the STEF12H60MA for >1sec then re-enabling > 1s does usually make it start-up without tripping (due to some residual-charge in capacitors assisting this?).

Looking at Vout / time, I found that there was a suddenly 2.5V 500us-wide dip in the linear-ramp Vout, when it reach around 8V. And this would often cause a premature-trip, so it never reached the full 12V of Vin.
Looking at voltage on CS pin, to see how current varied with time, there was a sharp transient-peak above it's startup limit (as it uses internal values, overriding the set value, during the start-up ramp phase).

[AScha.3]

you have a cap at SS pin ? value ?

+

on CS pin should be no cap.

 

[OwenR]

Yes, I have a 100nF on SS pin, for tSS=24ms - To ensure tSS is within the recommended 10-100ms range.
Without a capacitor, and the default tSS=300us, it won't even start-up into a 470uF Cout (even with no load).
I did try increasing C_SS to 220nF and also 470nF for a rather-longer 50ms / just over 100ms Soft-Start time. But I found having a longer soft-start (So voltage-ramp isn't climbing fast-enough to cope with transient dip / that occurs for long-enough to cause a n excess current-trip?) made the tripping slightly-worse and a large increase (>1000uF) to Cout was required, to avoid constant-tripping. But having large output capacitors was something I was trying to avoid.

Yes, (even though it's not in the datasheet - hence my question here) I subsequently tried adding a capacitor onto CS pin to try and filter-out the transient. And this seemed to be successful with a minimum value of 4.7nF (With 4.7uF required, to allow start-up into an Electronic load - Where large output capacitors alone do not appear to make any difference / even allow start-up with an electronic load set to only 100mA).

I have also tried adding a capacitor on the ON/PD pin, for a delayed-start, that some of the datasheet's graph were done with. But that hasn't really made any difference, and may be only to allow Vin to stabilise before it switches on.

[AScha.3]

still i dont understand all - you keep too many secrets. :)

what current is needed (real load? avg/peak demand?) ?

what current limit you set? if set 50A then ok?

SS with 220nF seem good.

and output maybe C-L-C , 220uF - 100uH-220uF  , to filter out load peaks

[OwenR]

The commercial receiver unit unfortunately doesn't really provide much detailed information regarding its current-profile, as it is mainly intended to operate off its supplied 12V 7A mains PSU / the unit has a max rating of 7.5A on its DC input socket. However, I've establish that the current builds up in stages, starting at around 1A, once input-voltage is high-enough (about 8V). It then jumps-up to several amps, once its uC / FPGA's boot up, never exceeding about half the stated 7A on average.
However, we haven't ever had a problem with it tripping once running, so the problem is just confined to initial boot-up, whilst its multiple PSU circuits are charging their output capacitors etc. 

So a 7.5A current limit has been set, as connector contacts are only rated at 8A.
If current limit is increased to double that, then initial tripping does cease, as this IC appears to have the same current-limit for transients as average current (unlike some rival ones, that do have provision for a higher transient current limit / ability to set delay time before it trips). 
But having a v.high current limit on this IC isn't really then protecting much, and the mains PSU for the unit already has a current-limit not that much higher.

An output-filter is an idea, and I may try this if I can find a suitable inductor to hand. Although it would involve having to find space for the extra high-current inductor on the existing board.

So I really hoped I could find an answer to my original question about whether it was OK to just add a filter capacitor across the CS pin resistor, as this seemed to be working OK so far. And using a high-enough value, also allowed full-testing of the circuit with an electronic load rather than having to use rather obsolete high-power rheostat's.
 

 

 

[AScha.3]

hey, the device use 3..6A , right? so set current limit to 10..14A and SS 220nF and it working reliable. right?

if device ever uses 8A - your tested limit- anyway is defective and a short peak up to 12A kills nothing, thats still alive.

so i see no problem here.

[OwenR]

Well by previously using a pre-set on the CLREF pin, finding a current limit around 15A was needed to start-up (even with no load) into around 7000uF output capacitance. But having it that high, also seemed to prevent the transient currents from tripping this, so then didn't need a high output capacitance.
However, having a current limit that high, also doesn't ensure the electrical-safety, that the eFuse was in the circuit to provide, as connector of the commercial unit only has a rating of 8A per pin.
Therefore, I wanted to keep the original current limit, and just provide a means of it not tripping on short-transients which it appears having large output capacitors was mainly meant to achieve - although little info in the datasheet about selecting the required amount, only a few performance graphs that stated some of the values they were obtained with.
And smoothing the sensed-current seemed a neater method, with bonus that with a high-enough value would also allow start-up into an electronic load. So I was just looking to see if that had been tried before / or wasn't recommended for a particular reason.