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Associate II
August 7, 2024
Solved

STP24DP05 IC queries

  • August 7, 2024
  • 1 reply
  • 2321 views

Hi Team,

We are using this STP24DP05 (24-bit constant current LED sink driver with output error detection) IC for a X*Y array of diodes to get high or low. The IC is interfaced with microcontroller using SDI pin of STP24DP05. We have some doubts kindly check-

1. How will the serial pin data transfers to  outputs R/G/B pin? does R1 , G1 & B1 gets data first then it goes to next R2,G2,B2? or it will first give data to R1-R8 then to next 8 bits goes to G1-G8 like that. 

2. Is LE/DM pin working as reset to all the pins? does the outputs of STP24DP05 gets refreshed when LE/DM is pulled down?

3. Can we keep OE pins as grounded ? 

 

Best answer by Peter BENSCH
  1. See data sheet, section 7.6, table 14 (shifter register data flow control).
  2. LE\DM is not a reset pin, but a Latch Enable pin enabling the latch circuit for a new set of data from the SDI chain.
  3. To be checked, but you need to switch at least OE-R\DM to enter the error detection mode.

Hope that helps?

Regards
/Peter

1 reply

Peter BENSCH
Peter BENSCHBest answer
Technical Moderator
August 12, 2024
  1. See data sheet, section 7.6, table 14 (shifter register data flow control).
  2. LE\DM is not a reset pin, but a Latch Enable pin enabling the latch circuit for a new set of data from the SDI chain.
  3. To be checked, but you need to switch at least OE-R\DM to enter the error detection mode.

Hope that helps?

Regards
/Peter

MeghlaAuthor
Associate II
August 27, 2024

Hi Peter,

Thanks for the reply.

1. We donot want error detection mode. In that case can we keep all three output enables as low ?

2. At what interval SDO comes out? what I understood from the timing diagram after sending out all the 24 parallel outputs it will send the SDO.

 

 

Peter BENSCH
Technical Moderator
August 27, 2024
  1. as described in section 7 of the data sheet: if you do not require error detection mode, do not set LE\DM and /OE-RE\DM to H at the same time and over some clock cycles

  2. yes, in normal mode SDO can be seen as an output of a shift register, i.e. the input data will occur after 24 clock cycles