TCPP01-M12 Cold-Start: How does the OVP and Gate Driver operate when VCC pin is strictly 0V?

[dimient23]

Hello everyone,

​I am designing a USB-C Sink-only application (5V/3A) using a standard STM32 MCU. My power architecture is as follows:

​Input: USB-C Connector (VBUS, CC1, CC2).

​Protection: TCPP01-M12 controlling an external N-channel MOSFET on the high side of VBUS.

​Regulation: A 3.3V LDO is connected downstream of the MOSFET.

​Supply: The 3.3V output from the LDO powers the MCU and the VCC/DB pins of the TCPP01-M12.

​The Constraints:

​The MCU's internal UCPD peripheral is not used (pins are allocated to other functions).

​The system must rely entirely on the autonomous hardware logic of the TCPP01-M12 for the initial power-up.

​The "Zero-VCC" Paradox:

I have a technical question regarding the Dead Battery startup sequence. When the system is first connected to a charger and is completely unpowered:

​VCC of the TCPP01-M12 is strictly 0V because the LDO hasn't started yet (the MOSFET is still open).

​DB pin is also at 0V.

​My Questions:

​Internal Powering: How does the TCPP01-M12 energize its internal OVP comparator and Charge Pump to drive the GATE pin when its own VCC pin is at 0V? Does the chip draw parasitic power from the VBUS_CTRL pin or the VBUS line to enable this initial logic?

​OVP Safety: How can we guarantee that the OVP logic is fully functional and capable of blocking the Gate Driver BEFORE the MOSFET closes, especially if a non-compliant 20V source is connected to this unpowered system?

​Charge Pump Mechanism: Could you clarify if the internal charge pump for the IN_GD (22nF bootstrap) is self-powered from the VBUS input during this "cold-start" phase?

​I am looking for a technical justification of the internal power rails during this transition to validate the safety of my hardware design.

​Thank you in advance for your support!

[Peter BENSCH]

Welcome @dimient23, to the community!

1. Internal powering (dead‑battery)
   In dead‑battery mode the TCPP01‑M12 powers its essential protection and gate‑driver logic directly from the VBUS side. It does not need VCC or DB to be present for basic operation.
2. OVP safety
   As soon as VBUS is present, the OVP comparator (supplied from VBUS) is already active. If VBUS is above the OVP threshold (e.g. 20V non‑compliant), the gate driver is blocked and the external MOSFET remains off, so the system stays isolated.
3. Charge pump during cold‑start
   The internal charge pump and the IN_GD capacitor are also supplied from the VBUS‑derived rail. They only start driving the GATE when VBUS is within the allowed range; if OVP is triggered, the charge pump is inhibited and GATE is kept low.

For a sink‑only, 5V/3A application using TCPP01‑M12 with MCU powered from a 3.3 V LDO downstream of the MOSFET, the safety concept is:

• Protection path and OVP logic are powered from VBUS, not from VCC, at plug‑in.
• MOSFET is kept off by default. It is only turned on after:
  • VBUS has been verified to be within the safe voltage range by the internal OVP comparator, and
  • the internal charge pump, powered from VBUS, drives GATE
• If an out‑of‑spec 20 V source is applied, OVP detects it first and prevents gate turn‑on, protecting the downstream 3.3 V rail and MCU even with VCC = 0 V.

Does it answer your questions?

Regards
/Peter

[dimient23]

Hi Peter,

​Thanks for the quick reply! That's exactly what I needed to hear to feel safe about the design.

​I have one last "curiosity" about how the chip actually does this. Since my VCC pin is at 0V when I first plug it in, I’m trying to visualize the internal "path" of the power.

​Does the TCPP01-M12 have a tiny internal regulator connected directly to the VBUS line to wake itself up? Or does it actually "steal" the tiny bit of current it needs through the VBUS_CTRL pin?

​I’m just trying to make sure I understand if there’s a "hidden" power connection to VBUS inside the silicon or if VBUS_CTRL is doing double duty as both a sensor and a power source.

​Thanks again for the help!

[AScha.3]

Hi,

start sequence is in ds ...:

#

> OVP Safety: How can we guarantee that the OVP logic is fully functional and capable of blocking the Gate Driver BEFORE the MOSFET closes, especially if a non-compliant 20V source is connected to this unpowered system?

OVP also shown:

 

[dimient23]

​Hi,

​Thanks for pointing that out! Those timing diagrams from the datasheet really help to visualize the sequence, especially seeing how the OVP is ready to block the Gate even before the system starts up.

​I’ll make sure to "Accept as Solution" once I’ve gathered all the details. Appreciate the help!