STM32 MCUs

hello team, I am facing a debug connection issue with STM32H723VGTx using STM32CubeIDE and ST-LINK.Issue details:MCU: STM32H723VGTxDebug tool: ST-LINK (OpenOCD via STM32CubeIDE)Interface: SWDReset mode: Software resetSWD frequency: 50 kHzObserved behavior:ST-LINK connects successfully.Cortex-M7 core is detected correctly.GDB server starts, but the debug session fails during memory access.Error message: Error: Failed to read memory at 0x5c001000 Error: auto_probe failed Error: Connect failedAdditional observations:Target voltage reported by ST-LINK is ~2.8 V.I already tried:Lowering SWD frequencyUsing software resetAdding monitor gdb_memory_map disable in debug startup commandsHalting on resetIssue still persists.Request:Could you please confirm:Whether this memory address (0x5C001000) access failure is related to power / AXI-D2 domain / debug configuration on STM32H723.If there are any recommended debug settings or patches for STM32H7 devices under these conditions.Whether mi

Hello Community,I tried with different boards (073, 093, 533, 401) to work with the SPI1 or SPI2.I used the examples, but there is no clock on an SPIx clock pin.e.g.   HAL_SPI_Transmit(&hspi1, SpiData, 2, 100); Has anybody a working STM32Cube porject to load in the STM32CubeIdefor  an SPI only master (no slave no DMA) in the send modus via MOSI pin.Thank youMichael  

Hello everyone!I am currently working on a speaker project that gets audio data from a microsd card over spi and sends it over i2s with DMA.I noticed that the main issue is the latency from the sd card so i got the adivce to use a triple pointer ring buffer.I searched for implementations on triple buffering with i2s but couldn't find a single one.I tried implementing it but it didn't work.(i added the code file to the post)Does anybody have good resources to learn this?

A new STM32 sub-family (as part of the 'H5 family) came out. They have everything but the kitchen sink. As far as I can tell, 'H5E4 and 'H5E5 differ only in that the higher one has USB-HS with PHY (the 'H5Fx are crypto-enabled variants, as usually) What's new is also the PLAY peripheral, which is a small programmable logic element, fully documented and configurable through registers. It's based around 16 simple logic elements (4-input LUT and an optional register), complete with an extensive input multiplexer matrix+filter, interconnected to a variety of peripherals (timers, DMA, ADC...) and also GPIO. I wonder, if there's a Disco around... JW  

After encountering an issue with a Hyperbus flash chip we moved our flash to what we thought would be a simpler OctoSpi Nor Flash. I am working with an STM32H7S7 chip with a NOR Flash S28HS512T. I cannot get the chip to communicate in the desired mode. Here are my steps so far:Configuration code from CubeMX:/* XSPI1 parameter configuration*/ hxspi1.Instance = XSPI1; hxspi1.Init.FifoThresholdByte = 4; hxspi1.Init.MemoryMode = HAL_XSPI_SINGLE_MEM; hxspi1.Init.MemoryType = HAL_XSPI_MEMTYPE_MICRON; hxspi1.Init.MemorySize = HAL_XSPI_SIZE_512MB; hxspi1.Init.ChipSelectHighTimeCycle = 3; hxspi1.Init.FreeRunningClock = HAL_XSPI_FREERUNCLK_DISABLE; hxspi1.Init.ClockMode = HAL_XSPI_CLOCK_MODE_0; hxspi1.Init.WrapSize = HAL_XSPI_WRAP_NOT_SUPPORTED; hxspi1.Init.ClockPrescaler = 3; hxspi1.Init.SampleShifting = HAL_XSPI_SAMPLE_SHIFT_NONE; hxspi1.Init.DelayHoldQuarterCycle = HAL_XSPI_DHQC_ENABLE; hxspi1.Init.ChipSelectBoundary = HAL_XSPI_BONDARYOF_NONE; hxspi1.Init.MaxTran = 0; hxspi1.In

Hello,I want to use the TW9992 NTSC/PAL Video Decoder for STM32N6 to transfer an NTSC camera (720x480 resolution) to the MCU via MIPI-CSI and display it on the screen. I have attached the code below.static void MX_DCMIPP_Init(void) { /* USER CODE BEGIN DCMIPP_Init 0 */ /* USER CODE END DCMIPP_Init 0 */ DCMIPP_CSI_PIPE_ConfTypeDef pCSI_PipeConfig = {0}; DCMIPP_CSI_ConfTypeDef pCSI_Config = {0}; DCMIPP_PipeConfTypeDef pPipeConfig = {0}; /* USER CODE BEGIN DCMIPP_Init 1 */ /* USER CODE END DCMIPP_Init 1 */ hdcmipp.Instance = DCMIPP; if (HAL_DCMIPP_Init(&hdcmipp) != HAL_OK) { Error_Handler(); } /** Pipe 0 Config */ pCSI_PipeConfig.DataTypeMode = DCMIPP_DTMODE_DTIDA; pCSI_PipeConfig.DataTypeIDA = DCMIPP_DT_RGB565; pCSI_PipeConfig.DataTypeIDB = DCMIPP_DT_RGB565; if (HAL_DCMIPP_CSI_PIPE_SetConfig(&hdcmipp, DCMIPP_PIPE0, &pCSI_PipeConfig) != HAL_OK) { Error_Handler(); } pCSI_Config.PHYBitrate = DCMIPP_CSI_PHY_BT_1600; pCSI_Config.DataLaneMapping =

I'm trying to download Cube MX, Cube Programmer, and Cube IDE. I registered and activated the license, but it won't download. I've tried using different browsers (Chrome, Firefox, Edge) without extensions. I accept the License Agreement, but nothing happens. I tried it as a guest user, too, but it won't download. I really need the programs, what should I do?

I am currently working on the LoRaWAN_END_NODE example project for a stm32WL . And I want to receive external data via uart and use the LoRaWan process continually, however I am getting problems. The UART is giving invalid data after the sequencer is being initialized.Edit: I have tried the suggestions below, I have put the gps into a task for the sequencer to run. I have also disabled low power mode. I still get invalid data from the UART that I don't receive when the sequencer is not on.Is this a clock issue? Any ideas?

Hi,I created a blank project for STM32U5G9J-DK2 and in process of programming the board, GfxDesigner generates 400MB file intflash.elf. With GfxDesigner 4.24.1 it is 4MB.Why 4.26.1 generates  intflash.elf so large ? A bug ?Thanks  

.clangd is constantly being modified appending the same compileflags: CompileFlags: Add: - '-ferror-limit=0' - '-Wno-implicit-int' CompilationDatabase: CM7/build Diagnostics: Suppress: - unused-includes - unknown_typename - unknown_typename_suggest - typename_requires_specqual If: PathMatch: CM7/.* --- CompileFlags: Add: - '-ferror-limit=0' - '-Wno-implicit-int' CompilationDatabase: CM4/build Diagnostics: Suppress: - unused-includes - unknown_typename - unknown_typename_suggest - typename_requires_specqual If: PathMatch: CM4/.* --- CompileFlags: Add: - '-ferror-limit=0' - '-Wno-implicit-int' CompilationDatabase: CM4/build Diagnostics: Suppress: - unused-includes - unknown_typename - unknown_typename_suggest - typename_requires_specqual If: PathMatch: CM4/.* --- CompileFlags: Add: - '-ferror-limit=0' - '-Wno-implicit-int' CompilationDatabase: CM7/build Diagnostics: Suppress: - unused-includes - unknown_typename - unknown_typename_suggest

I have a simple question. Is it possible to use TouchGFX+ThreadX with enabled Ethernet and NETXDuo SNTP client at a same time in STM32N6570-DK board? In other words: take the TouchGFX ClockExample then in CUBEMX enable the Ethernet port with NETXDuo-SNTP server. Will it cause pin conflict? I mean the Ethernet uses the same pins as LTDC. I enabled the Ethernet in ClockExample project and I got blank screen and the app was frozen. After removing Ethernet from the project, the analog and digital clocks appeared again on the display. Thanks, Louis

We used to define STM32 pinout in STM32CubeMx since it's aware of all the possiblilities of the MCU.Then we manually need to transfer the pnout into Altium Designer Schematic. And to keep those in sync when design changes.So we want to automate that step if possible.Thus the question: How can I Import pinout generated from STM32CubeMx into Altium Designer Schematic.

Good day,I am writing firmware for a custom board using the STM32G0B1KET6 and am experiencing issues related to writing a serial number to the internal flash.As far as I can tell, this MCU has 512 KB of flash split into 2 banks of 128 pages (each page is 2 KB). I am attempting to write to the last page of the first bank (Page 127 @ 0x803F800).I have modified the linker file to reduce the flash area used by my application code like so:MEMORY { RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 144K FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 64K }Here is my flash writing function. uint8_t Flash_Write(uint32_t startAddress, uint64_t data) { __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR); __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_BSY1); __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_BSY2); __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGSERR); __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGAERR); __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_CFGBSY); if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_CFGBSY) == 1) { return 0; } HAL_StatusTypeDef status;

Hi All,I am beginner to drones. We assembled one drone using STEVAL FCU. 002. board ,  recommended set. of motors and. propellers along with battery. We Chose different. frame.  than. one recommended . It is smaller in size. While flying , vertical take. off. could. not be achieved.Can someone guide please ?Motor connections , Clock wise. ,  anti clock wise in reference. to alignment. of. the boards are checked. already.It is ST board. so. come equipped with all driver , frimware etc.Thanks in advance.Early and accurate response is. appreciated.Regards, 

hello ST Community,where can I set it to avoid generating the file "startup_stm32l5...zetxq.s" during compilation and debugging in the stm32CubeIDE environment and also how to avoid that the space bar "|" when editing the line of code of 'main.c' is automatically moved to the last line of code of 'main.c' during compilation and debugging. Where should I set it to avoid all this?Thanks so much for your support

Im trying to setup FreeRTOS with the new STM32N6.According to https://github.com/STMicroelectronics/x-cube-freertos, the new Nucleo board for the STM32N6 is mentioned as supported.But in the CubeIDE, when trying to enable the FreeRTOS middleware, it says that the new nucleo board is not supported. And the docs also only mention AzureRTOS as supported.Is FreeRTOS supported through the CubeIDE? Or only AzureRTOS? 

Hello,I recently came across an ST article describing a Condition-Based Monitoring architecture using a dual-MCU approach, with an STM32L476RG handling signal processing (and potentially edge AI), and an STM32WL dedicated to network connectivity.I find this architecture very interesting and relevant for a project I’m currently exploring, but I would like to better understand what level of support and resources are available from ST for implementing such a solution in practice.In particular, I have a few questions:Does ST provide official support or reference designs for this kind of dual-MCU architecture (STM32L4 + STM32WL)?Are there any example projects, application notes, or firmware packages that demonstrate communication between the two MCUs in this context?Regarding FUOTA (Firmware Update Over The Air), are there existing solutions or middleware provided by ST that support this setup, especially with STM32WL acting as the communication node?Are there recommended tools, libraries,

Newest AN4879 does not list STM32C5 as applicable products.

Hi everyone,I am trying to setup DCMIPP Pipe0 to read data from 256x192 pixel sensor by 16 data lines.Seems everything configured and working fine except of transfer data to destination buffer.DCMIPP frame counter is increasing. Pipe0 dump counter is 0x18000 (256x192x2).HAL_DCMIPP_PIPE_Start return HAL_OK.Pipe0 packer memory address register is qual to Pipe0 memory status address register and correspond to address of buffer in RAM.I checked that DCMIPP don't write zero values by initing frame buffer with 0xFF and it wasn't changed to zeros. I am sure that sensor is working because of frame counter, dump counter, checking lines with oscilloscope and it is working with other pcb with STM32H7 and DCMI interface.  Also I validated that debugger read frame buffer correctly by sending it thought uart. Source code is simple, generated by cube init than I2C configuration of sensor(validated) and than reading in loop with delay:while (1){    HAL

Hi Team, I am designing a custom PCB using STM32H753 and planning to use the QUADSPI peripheral for external memory. My use case is data read/write (indirect mode) — not XIP or memory-mapped execution. While working in STM32CubeMX, I came across some configurations that are confusing, and I’d like to clarify the actual hardware behavior. 1. Dual Bank vs Chip Select behavior In CubeMX, I can configure: QuadSPI Mode: Dual Bank with Quad Lines Chip Select options: Enable Chip Select 1 for both banks Enable Chip Select 2 for both banks Enable Chip Select for each bank My understanding: NCS → Bank1 NCS2 → Bank2 Questions: If I select “Enable Chip Select 1 for both banks”, does this mean: Only one physical flash is used and banks are logical partitions? Or is there any way two physical memories are still utilized? What is the exact meaning of “bank” in this context (hardware vs logical)? 2. BK1_IOx and BK2_IOx pins confusion CubeMX exposes: QUADSPI_BK1_IO0

I have recently installed STM32CubeIDE 2.1.1 on linux and opened an existing project workspace. Everything looks fine except the integration with CubeMX for ioc files (which I believe is now by-design). The problem I have is after going to eclipse marketplace and installing Subclipse, it installs fine, then after restarting it goes into an endless loop saying the application is not responding. Finally, I got a message about "Failed to load JavaHL Library.", but I'm not sure if that's the real cause as dismissing the dialog reverts back to the application not responding loop.  Reinstalling the IDE does not help. The only way I've found to get the IDE to work is by removing the stm32 folder under $HOME/.eclipse, but this doesn't correct the issue with subclipse or its connection to subversion. Any help much appreciated.

Hi,I have STM32H755ZIT3 controller, and I am tying to read voltage sensor AMC1333M10 and sensor has internal clock of 10 MHz . I am trying to read on controller DFSDM channel 7, core M4 with clock 64 MHz . Is this practically possible to read in such a configuration ? As when I read the value(dfsdm_buffer), it is always 7 (~0) whether there are voltages on the terminal or not.Code: // start HAL_DFSDM_FilterRegularStart_DMA(&hdfsdm1_filter0, (int32_t *)dfsdm_buffer, BUFFER_SIZE); // callback : void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { ... }Following is my configuration for DFSDM in MX : Channel 7 : "PDM/SPI input form ch7 and external clock"Channel 7 :Channel 7 Parameters:Type : "SPI with rising edge"Offset : 0Right Bit Shift : 0x00Analog watchdog parameters:Filter Order: "Sinc 3 filter type"Oversampling: 1Filter 0:regular channel selection:regular channel selection: "Channel 7"Continuous Mode: "Continuous Mode"Trigg

I am using ST’s Motor Control Workbench (MCW) version 6.3.2 to control a sliding door. I am using PMSM as motor and FOC as control method. PMSM has 10 pole pairs and there is a 1024 ppr incremental quadrature encoder on it (has not index pin). I am using Nucleo-G474RE, STEVAL-IHM023V3 and X-Nucleo-IHM09M2 boards. I am having trouble with encoder alignment. if I'm not mistaken, ST MCW uses “move till aligned with phase A” method (see attachment) as the encoder alignment. But i have a mechanical limit and this will not allow the motor to perform the needed alignment movements. I have posted this in the motor control forum. Not answered yet (https://community.st.com/t5/stm32-mcus-motor-control/incremental-encoder-alignment-problem/td-p/775343) Does ST have any plans to update MCW software to include the motionless start method into speed sensing configuration in the near future? Can anyboady give/share source code/flow chart etc.? Any information you provide will be gl

Hi,I am working with the STM32N6 series MCU on the STM32N6570-DK board and have encountered a pin multiplexing conflict.As per the schematics and datasheet:PA15 (JTDI) and PB4 (JNRST) are multiplexed with LTDC signalsThese pins do not appear to have alternate mappingsMy use case requires:LTDC for driving the displayJTAG for debugging (full JTAG, not just SWD)However, enabling LTDC conflicts with the JTAG interface, specifically JTDI.I have a few questions:Is there any supported way to use both LTDC and full JTAG simultaneously on STM32N6?Are there any alternate pin mappings or remap options available that are not obvious from CubeMX?Is dynamic switching (e.g., using JTAG during debug and reconfiguring pins for LTDC at runtime) a viable or recommended approach?Are there any hardware workarounds or recommended debug strategies for this scenario?I understand that switching to SWD avoids this issue, but I would like to confirm if full JTAG usage is fundamentally incompatible with LTDC on t

Hello,I found a CubeMX database issue affecting STM32H747 dual-core projects using FreeRTOS with CMSIS-RTOS V2.EnvironmentMCU: STM32H747Cube/HAL: STM32CubeH7 1.13.xCubeMX: 6.17FreeRTOS: 10.6.2ProblemTwo FreeRTOS configuration parameters are not present in the MicroXplorer Configuration settings and are not retained in the internal IOC model:configUSE_SB_COMPLETED_CALLBACK configUSE_MINI_LIST_ITEMBecause of that, code generation can produce invalid output in FreeRTOSConfig.h such as:#define configUSE_MINI_LIST_ITEM ( valueNotSetted ) #define configUSE_SB_COMPLETED_CALLBACK ( valueNotSetted )This breaks the build and/or downstream FreeRTOS code.Editing the .ioc manually does not solve it permanently, because CubeMX overwrites the .ioc on regeneration.Adding manual defines in USER CODE blocks is only a local workaround and does not fix the root cause.Root cause foundThe issue appears to be in the CubeMX FreeRTOS mode database, not in the generated project itself.For STM32H747, CubeMX uses